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Alex Forencich 19b1af0388 Update Xilinx UltraScale shims to support TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-04 00:46:07 -07:00
..
dma_client_axis_sink
Clean up testbench parametrization
2022-06-05 14:25:28 -07:00
dma_client_axis_source
Clean up testbench parametrization
2022-06-05 14:25:28 -07:00
dma_if_axi
Update AXI DMA IF tests
2022-06-05 14:29:16 -07:00
dma_if_axi_rd
Update AXI DMA IF tests
2022-06-05 14:29:16 -07:00
dma_if_axi_wr
Update AXI DMA IF tests
2022-06-05 14:29:16 -07:00
dma_if_pcie_rd
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
dma_if_pcie_us
Clean up testbench parametrization
2022-06-05 14:25:28 -07:00
dma_if_pcie_us_rd
Clean up testbench parametrization
2022-06-05 14:25:28 -07:00
dma_if_pcie_us_wr
Clean up testbench parametrization
2022-06-05 14:25:28 -07:00
dma_if_pcie_wr
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axi_master
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axi_master_rd
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axi_master_wr
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axil_master
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axil_master_minimal
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_msix
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_s10_if
Update Stratix 10 H-tile/L-tile shim to support segments
2022-07-02 23:48:46 -07:00
pcie_s10_if_rx
Update Stratix 10 H-tile/L-tile shim to support segments
2022-07-02 23:48:46 -07:00
pcie_s10_if_tx
Update Stratix 10 H-tile/L-tile shim to support segments
2022-07-02 23:48:46 -07:00
pcie_tlp_demux
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_demux_bar
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_fifo
Add segmented PCIe TLP FIFO module
2022-07-02 15:35:57 -07:00
pcie_tlp_fifo_mux
Add PCIe TLP FIFO mux module
2022-07-02 23:41:27 -07:00
pcie_tlp_mux
Update PCIe TLP mux to handle multiple segments
2022-07-02 23:40:35 -07:00
pcie_us_axi_dma
Update testbenches for new version of cocotbext-pcie
2022-06-05 13:26:27 -07:00
pcie_us_axi_dma_rd
Update testbenches for new version of cocotbext-pcie
2022-06-05 13:26:27 -07:00
pcie_us_axi_dma_wr
Update testbenches for new version of cocotbext-pcie
2022-06-05 13:26:27 -07:00
pcie_us_axi_master
Update testbenches for new version of cocotbext-pcie
2022-06-05 13:26:27 -07:00
pcie_us_axi_master_rd
Update testbenches for new version of cocotbext-pcie
2022-06-05 13:26:27 -07:00
pcie_us_axi_master_wr
Update testbenches for new version of cocotbext-pcie
2022-06-05 13:26:27 -07:00
pcie_us_axil_master
Update testbenches for new version of cocotbext-pcie
2022-06-05 13:26:27 -07:00
pcie_us_if
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_if_cc
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_if_cq
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_if_rc
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_if_rq
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
axi.py
Update AXI simulation model
2020-07-02 21:28:35 -07:00
axil.py
Add Ultascale PCIe AXI lite master module and testbenches
2018-09-25 21:09:20 -07:00
axis_ep.py
Add AXI stream endpoint model
2018-09-25 20:55:44 -07:00
dma_psdp_ram.py
Use start_soon instead of fork
2021-12-10 17:44:37 -08:00
dma_ram.py
Add segmented DMA RAM simulation model
2019-10-08 15:14:32 -07:00
Makefile
Add cocotb testbenches
2020-12-19 14:10:57 -08:00
pcie_if.py
Add strobe outputs to shims
2022-06-07 14:23:24 -07:00
pcie_us.py
Placeholder values for flow control credit outputs
2019-12-06 19:16:05 -08:00
pcie_usp.py
Placeholder values for flow control credit outputs
2019-12-06 19:16:05 -08:00
pcie.py
Improve BAR initialization
2020-07-24 22:54:55 -07:00
test_dma_client_axis_sink_128_64.py
Update python parameter computation to match verilog clog2
2019-11-24 00:01:33 -08:00
test_dma_client_axis_sink_128_64.v
Add AXI stream sink DMA client module and testbench
2019-10-12 22:35:57 -07:00
test_dma_client_axis_sink_512_64.py
Update python parameter computation to match verilog clog2
2019-11-24 00:01:33 -08:00
test_dma_client_axis_sink_512_64.v
Add AXI stream sink DMA client module and testbench
2019-10-12 22:35:57 -07:00
test_dma_client_axis_source_128_64.py
Update python parameter computation to match verilog clog2
2019-11-24 00:01:33 -08:00
test_dma_client_axis_source_128_64.v
Add AXI stream source DMA client module and testbench
2019-10-12 22:34:15 -07:00
test_dma_client_axis_source_512_64.py
Update python parameter computation to match verilog clog2
2019-11-24 00:01:33 -08:00
test_dma_client_axis_source_512_64.v
Add AXI stream source DMA client module and testbench
2019-10-12 22:34:15 -07:00
test_dma_if_pcie_us_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_64.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_64.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_128.py
Remove extraneous character
2019-12-07 14:36:32 -08:00
test_dma_if_pcie_us_rd_128.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_512.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_rd_512.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_64.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_64.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_128.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_128.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_512.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_dma_if_pcie_us_wr_512.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_64.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_64.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_128.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_128.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_512.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_rd_512.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_64.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_64.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_128.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_128.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_256.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_256.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_512.py
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_dma_wr_512.v
Add credit-based flow control to DMA cores
2019-12-06 23:24:36 -08:00
test_pcie_us_axi_master_64.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_64.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_128.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_128.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_256.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_256.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_64.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_64.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_128.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_128.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_256.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_256.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_rd_512.py
Update AXI master modules to support 512 bit interface
2019-10-14 16:20:46 -07:00
test_pcie_us_axi_master_rd_512.v
Update AXI master modules to support 512 bit interface
2019-10-14 16:20:46 -07:00
test_pcie_us_axi_master_wr_64.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_64.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_128.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_128.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_256.py
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_256.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axi_master_wr_512.py
Update AXI master modules to support 512 bit interface
2019-10-14 16:20:46 -07:00
test_pcie_us_axi_master_wr_512.v
Update AXI master modules to support 512 bit interface
2019-10-14 16:20:46 -07:00
test_pcie_us_axil_master_64.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie_us_axil_master_64.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axil_master_128.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie_us_axil_master_128.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axil_master_256.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie_us_axil_master_256.v
Parametrize tuser signal widths
2019-09-26 23:30:03 -07:00
test_pcie_us_axil_master_512.py
Update AXI lite master module to support 512 bit interface
2019-10-14 15:58:38 -07:00
test_pcie_us_axil_master_512.v
Update AXI lite master module to support 512 bit interface
2019-10-14 15:58:38 -07:00
test_pcie_us.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie_usp.py
Add USPcieFrame intermediate format
2019-10-12 18:01:39 -07:00
test_pcie.py
Don't use traceSignals
2019-07-14 21:45:10 -07:00