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95 lines
3.3 KiB
Makefile
95 lines
3.3 KiB
Makefile
# Copyright (c) 2022 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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TOPLEVEL_LANG = verilog
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SIM ?= icarus
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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export PORTS ?= 4
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DUT = pcie_tlp_mux
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WRAPPER = $(DUT)_wrap_$(PORTS)
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TOPLEVEL = $(WRAPPER)
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MODULE = test_$(DUT)
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VERILOG_SOURCES += $(WRAPPER).v
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VERILOG_SOURCES += ../../rtl/$(DUT).v
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# module parameters
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export PARAM_TLP_DATA_WIDTH ?= 64
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export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
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export PARAM_TLP_HDR_WIDTH ?= 128
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export PARAM_SEQ_NUM_WIDTH ?= 6
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export PARAM_TLP_SEG_COUNT ?= 1
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export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0
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export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).SEQ_NUM_WIDTH=$(PARAM_SEQ_NUM_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
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COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
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COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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COMPILE_ARGS += -s iverilog_dump
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endif
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
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COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
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COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
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COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
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COMPILE_ARGS += -GSEQ_NUM_WIDTH=$(PARAM_SEQ_NUM_WIDTH)
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COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
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COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
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COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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$(WRAPPER).v: ../../rtl/$(DUT)_wrap.py
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$< -p $(PORTS)
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
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echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
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echo 'end' >> $@
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echo 'endmodule' >> $@
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clean::
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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@rm -rf *_wrap_*.v
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