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282 lines
9.7 KiB
Verilog
282 lines
9.7 KiB
Verilog
/*
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Copyright 2021, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PTP hardware clock
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*/
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module mqnic_ptp_clock #
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(
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parameter PTP_PERIOD_NS_WIDTH = 4,
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parameter PTP_OFFSET_NS_WIDTH = 32,
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parameter PTP_FNS_WIDTH = 32,
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parameter PTP_PERIOD_NS = 4'd4,
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parameter PTP_PERIOD_FNS = 32'd0,
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parameter PTP_PEROUT_ENABLE = 0,
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parameter PTP_PEROUT_COUNT = 1,
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parameter REG_ADDR_WIDTH = 7,
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parameter REG_DATA_WIDTH = 32,
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parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
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parameter RB_BASE_ADDR = 0,
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parameter RB_NEXT_PTR = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Register interface
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*/
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input wire [REG_ADDR_WIDTH-1:0] reg_wr_addr,
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input wire [REG_DATA_WIDTH-1:0] reg_wr_data,
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input wire [REG_STRB_WIDTH-1:0] reg_wr_strb,
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input wire reg_wr_en,
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output wire reg_wr_wait,
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output wire reg_wr_ack,
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input wire [REG_ADDR_WIDTH-1:0] reg_rd_addr,
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input wire reg_rd_en,
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output wire [REG_DATA_WIDTH-1:0] reg_rd_data,
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output wire reg_rd_wait,
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output wire reg_rd_ack,
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/*
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* PTP clock
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*/
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output wire ptp_pps,
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output wire [95:0] ptp_ts_96,
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output wire ptp_ts_step
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);
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localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
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// check configuration
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initial begin
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if (REG_DATA_WIDTH != 32) begin
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$error("Error: Register interface width must be 32 (instance %m)");
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$finish;
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end
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if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
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$error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (REG_ADDR_WIDTH < 7) begin
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$error("Error: Register address width too narrow (instance %m)");
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$finish;
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end
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if (RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 7'h60) begin
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$error("Error: RB_NEXT_PTR overlaps block (instance %m)");
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$finish;
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end
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end
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// control registers
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reg reg_wr_ack_reg = 1'b0;
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reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0;
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reg reg_rd_ack_reg = 1'b0;
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reg [95:0] get_ptp_ts_96_reg = 0;
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reg [95:0] set_ptp_ts_96_reg = 0;
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reg set_ptp_ts_96_valid_reg = 0;
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reg [PTP_PERIOD_NS_WIDTH-1:0] set_ptp_period_ns_reg = 0;
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reg [PTP_FNS_WIDTH-1:0] set_ptp_period_fns_reg = 0;
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reg set_ptp_period_valid_reg = 0;
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reg [PTP_OFFSET_NS_WIDTH-1:0] set_ptp_offset_ns_reg = 0;
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reg [PTP_FNS_WIDTH-1:0] set_ptp_offset_fns_reg = 0;
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reg [15:0] set_ptp_offset_count_reg = 0;
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reg set_ptp_offset_valid_reg = 0;
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wire set_ptp_offset_active;
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assign reg_wr_wait = 1'b0;
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assign reg_wr_ack = reg_wr_ack_reg;
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assign reg_rd_data = reg_rd_data_reg;
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assign reg_rd_wait = 1'b0;
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assign reg_rd_ack = reg_rd_ack_reg;
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always @(posedge clk) begin
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reg_wr_ack_reg <= 1'b0;
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reg_rd_data_reg <= 0;
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reg_rd_ack_reg <= 1'b0;
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set_ptp_ts_96_valid_reg <= 1'b0;
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set_ptp_period_valid_reg <= 1'b0;
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set_ptp_offset_valid_reg <= 1'b0;
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if (reg_wr_en && !reg_wr_ack_reg) begin
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// write operation
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reg_wr_ack_reg <= 1'b1;
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case ({reg_wr_addr >> 2, 2'b00})
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// PHC
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RBB+7'h30: set_ptp_ts_96_reg[15:0] <= reg_wr_data; // PTP set fns
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RBB+7'h34: set_ptp_ts_96_reg[45:16] <= reg_wr_data; // PTP set ns
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RBB+7'h38: set_ptp_ts_96_reg[79:48] <= reg_wr_data; // PTP set sec l
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RBB+7'h3C: begin
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// PTP set sec h
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set_ptp_ts_96_reg[95:80] <= reg_wr_data;
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set_ptp_ts_96_valid_reg <= 1'b1;
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end
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RBB+7'h40: set_ptp_period_fns_reg <= reg_wr_data; // PTP period fns
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RBB+7'h44: begin
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// PTP period ns
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set_ptp_period_ns_reg <= reg_wr_data;
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set_ptp_period_valid_reg <= 1'b1;
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end
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RBB+7'h50: set_ptp_offset_fns_reg <= reg_wr_data; // PTP offset fns
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RBB+7'h54: set_ptp_offset_ns_reg <= reg_wr_data; // PTP offset ns
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RBB+7'h58: begin
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// PTP offset count
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set_ptp_offset_count_reg <= reg_wr_data;
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set_ptp_offset_valid_reg <= 1'b1;
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end
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default: reg_wr_ack_reg <= 1'b0;
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endcase
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end
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if (reg_rd_en && !reg_rd_ack_reg) begin
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// read operation
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reg_rd_ack_reg <= 1'b1;
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case ({reg_rd_addr >> 2, 2'b00})
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// PHC
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RBB+7'h00: reg_rd_data_reg <= 32'h0000C080; // PHC: Type
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RBB+7'h04: reg_rd_data_reg <= 32'h00000100; // PHC: Version
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RBB+7'h08: reg_rd_data_reg <= RB_NEXT_PTR; // PHC: Next header
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RBB+7'h0C: begin
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// PHC features
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reg_rd_data_reg[7:0] <= PTP_PEROUT_ENABLE ? PTP_PEROUT_COUNT : 0;
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reg_rd_data_reg[15:8] <= 0;
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reg_rd_data_reg[23:16] <= 0;
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reg_rd_data_reg[31:24] <= 0;
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end
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RBB+7'h10: reg_rd_data_reg <= ptp_ts_96[15:0]; // PTP cur fns
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RBB+7'h14: reg_rd_data_reg <= ptp_ts_96[45:16]; // PTP cur ns
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RBB+7'h18: reg_rd_data_reg <= ptp_ts_96[79:48]; // PTP cur sec l
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RBB+7'h1C: reg_rd_data_reg <= ptp_ts_96[95:80]; // PTP cur sec h
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RBB+7'h20: begin
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// PTP get fns
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get_ptp_ts_96_reg <= ptp_ts_96;
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reg_rd_data_reg <= ptp_ts_96[15:0];
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end
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RBB+7'h24: reg_rd_data_reg <= get_ptp_ts_96_reg[45:16]; // PTP get ns
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RBB+7'h28: reg_rd_data_reg <= get_ptp_ts_96_reg[79:48]; // PTP get sec l
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RBB+7'h2C: reg_rd_data_reg <= get_ptp_ts_96_reg[95:80]; // PTP get sec h
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RBB+7'h30: reg_rd_data_reg <= set_ptp_ts_96_reg[15:0]; // PTP set fns
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RBB+7'h34: reg_rd_data_reg <= set_ptp_ts_96_reg[45:16]; // PTP set ns
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RBB+7'h38: reg_rd_data_reg <= set_ptp_ts_96_reg[79:48]; // PTP set sec l
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RBB+7'h3C: reg_rd_data_reg <= set_ptp_ts_96_reg[95:80]; // PTP set sec h
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RBB+7'h40: reg_rd_data_reg <= set_ptp_period_fns_reg; // PTP period fns
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RBB+7'h44: reg_rd_data_reg <= set_ptp_period_ns_reg; // PTP period ns
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RBB+7'h48: reg_rd_data_reg <= PTP_PERIOD_FNS; // PTP nom period fns
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RBB+7'h4C: reg_rd_data_reg <= PTP_PERIOD_NS; // PTP nom period ns
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RBB+7'h50: reg_rd_data_reg <= set_ptp_offset_fns_reg; // PTP offset fns
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RBB+7'h54: reg_rd_data_reg <= set_ptp_offset_ns_reg; // PTP offset ns
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RBB+7'h58: reg_rd_data_reg <= set_ptp_offset_count_reg; // PTP offset count
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RBB+7'h5C: reg_rd_data_reg <= set_ptp_offset_active; // PTP offset status
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default: reg_rd_ack_reg <= 1'b0;
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endcase
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end
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if (rst) begin
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reg_wr_ack_reg <= 1'b0;
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reg_rd_ack_reg <= 1'b0;
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end
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end
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// PTP clock
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ptp_clock #(
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.PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
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.OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
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.FNS_WIDTH(PTP_FNS_WIDTH),
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.PERIOD_NS(PTP_PERIOD_NS),
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.PERIOD_FNS(PTP_PERIOD_FNS),
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.DRIFT_ENABLE(0)
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)
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ptp_clock_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Timestamp inputs for synchronization
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*/
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.input_ts_96(set_ptp_ts_96_reg),
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.input_ts_96_valid(set_ptp_ts_96_valid_reg),
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.input_ts_64(0),
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.input_ts_64_valid(1'b0),
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/*
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* Period adjustment
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*/
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.input_period_ns(set_ptp_period_ns_reg),
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.input_period_fns(set_ptp_period_fns_reg),
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.input_period_valid(set_ptp_period_valid_reg),
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/*
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* Offset adjustment
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*/
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.input_adj_ns(set_ptp_offset_ns_reg),
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.input_adj_fns(set_ptp_offset_fns_reg),
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.input_adj_count(set_ptp_offset_count_reg),
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.input_adj_valid(set_ptp_offset_valid_reg),
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.input_adj_active(set_ptp_offset_active),
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/*
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* Drift adjustment
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*/
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.input_drift_ns(0),
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.input_drift_fns(0),
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.input_drift_rate(0),
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.input_drift_valid(0),
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/*
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* Timestamp outputs
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*/
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.output_ts_96(ptp_ts_96),
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.output_ts_64(),
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.output_ts_step(ptp_ts_step),
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/*
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* PPS output
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*/
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.output_pps(ptp_pps)
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);
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endmodule
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`resetall
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