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285 lines
10 KiB
Verilog
285 lines
10 KiB
Verilog
/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Transmit scheduler (round-robin)
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*/
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module tx_scheduler_rr #
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(
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parameter AXIL_DATA_WIDTH = 32,
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parameter AXIL_ADDR_WIDTH = 16,
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
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parameter AXI_DMA_LEN_WIDTH = 16,
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parameter REQ_TAG_WIDTH = 8,
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parameter QUEUE_INDEX_WIDTH = 6
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Transmit request output (queue index)
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*/
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue,
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output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag,
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output wire m_axis_tx_req_valid,
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input wire m_axis_tx_req_ready,
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/*
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* Transmit request status input
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*/
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input wire [AXI_DMA_LEN_WIDTH-1:0] s_axis_tx_req_status_len,
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input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_status_tag,
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input wire s_axis_tx_req_status_valid,
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/*
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* Doorbell input
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*/
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input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_doorbell_queue,
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input wire s_axis_doorbell_valid,
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/*
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* AXI-Lite slave interface
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*/
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
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input wire [2:0] s_axil_awprot,
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input wire s_axil_awvalid,
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output wire s_axil_awready,
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input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
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input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
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input wire s_axil_wvalid,
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output wire s_axil_wready,
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output wire [1:0] s_axil_bresp,
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output wire s_axil_bvalid,
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input wire s_axil_bready,
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input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [2:0] s_axil_arprot,
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input wire s_axil_arvalid,
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output wire s_axil_arready,
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output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
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output wire [1:0] s_axil_rresp,
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output wire s_axil_rvalid,
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input wire s_axil_rready
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);
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parameter VALID_ADDR_WIDTH = AXIL_ADDR_WIDTH - $clog2(AXIL_STRB_WIDTH);
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parameter WORD_WIDTH = AXIL_STRB_WIDTH;
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parameter WORD_SIZE = AXIL_DATA_WIDTH/WORD_WIDTH;
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// check configuration
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initial begin
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if (AXIL_ADDR_WIDTH < 18) begin // TODO
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$error("Error: AXI address width too narrow");
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$finish;
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end
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if (AXIL_DATA_WIDTH != 32) begin
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$error("Error: AXI data width must be 32");
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$finish;
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end
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if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
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$error("Error: Interface requires byte (8-bit) granularity");
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$finish;
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end
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end
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parameter QUEUE_WIDTH = 2**QUEUE_INDEX_WIDTH;
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reg [QUEUE_WIDTH-1:0] queue_enable_reg = 0, queue_enable_next;
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reg [QUEUE_WIDTH-1:0] queue_active_reg = 0;
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reg [QUEUE_WIDTH-1:0] queue_mask_reg = 0;
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reg [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue_reg = 0;
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reg [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag_reg = 0;
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reg m_axis_tx_req_valid_reg = 1'b0;
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wire queue_valid;
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wire [QUEUE_INDEX_WIDTH-1:0] queue_index;
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priority_encoder #(
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.WIDTH(QUEUE_WIDTH),
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.LSB_PRIORITY("HIGH")
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)
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priority_encoder_inst (
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.input_unencoded(queue_active_reg & queue_enable_reg),
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.output_valid(queue_valid),
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.output_encoded(queue_index),
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.output_unencoded()
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);
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wire masked_queue_valid;
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wire [QUEUE_INDEX_WIDTH-1:0] masked_queue_index;
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priority_encoder #(
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.WIDTH(QUEUE_WIDTH),
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.LSB_PRIORITY("HIGH")
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)
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priority_encoder_masked (
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.input_unencoded(queue_active_reg & queue_mask_reg & queue_enable_reg),
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.output_valid(masked_queue_valid),
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.output_encoded(masked_queue_index),
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.output_unencoded()
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);
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always @(posedge clk) begin
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if (s_axis_doorbell_valid) begin
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queue_active_reg <= queue_active_reg | (1 << s_axis_doorbell_queue);
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end
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// TODO deactivate idle queues
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m_axis_tx_req_valid_reg <= m_axis_tx_req_valid_reg && !m_axis_tx_req_ready;
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if (!m_axis_tx_req_valid || m_axis_tx_req_ready) begin
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if (queue_valid) begin
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if (masked_queue_valid) begin
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m_axis_tx_req_queue_reg <= masked_queue_index;
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m_axis_tx_req_valid_reg <= 1'b1;
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queue_mask_reg <= {QUEUE_WIDTH{1'b1}} << (masked_queue_index + 1);
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end else begin
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m_axis_tx_req_queue_reg <= queue_index;
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m_axis_tx_req_valid_reg <= 1'b1;
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queue_mask_reg <= {QUEUE_WIDTH{1'b1}} << (queue_index + 1);
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end
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end
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end
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if (rst) begin
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queue_active_reg <= 0;
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queue_mask_reg <= 0;
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end
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end
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// control registers
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reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
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reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
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reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
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reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
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reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, s_axil_rdata_next;
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reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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assign m_axis_tx_req_queue = m_axis_tx_req_queue_reg;
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assign m_axis_tx_req_tag = m_axis_tx_req_tag_reg;
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assign m_axis_tx_req_valid = m_axis_tx_req_valid_reg;
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assign s_axil_awready = s_axil_awready_reg;
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assign s_axil_wready = s_axil_wready_reg;
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assign s_axil_bresp = 2'b00;
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assign s_axil_bvalid = s_axil_bvalid_reg;
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assign s_axil_arready = s_axil_arready_reg;
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assign s_axil_rdata = s_axil_rdata_reg;
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assign s_axil_rresp = 2'b00;
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assign s_axil_rvalid = s_axil_rvalid_reg;
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always @* begin
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s_axil_awready_next = 1'b0;
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s_axil_wready_next = 1'b0;
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s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
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s_axil_arready_next = 1'b0;
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s_axil_rdata_next = s_axil_rdata_reg;
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s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;
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queue_enable_next = queue_enable_reg;
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if (s_axil_awvalid && s_axil_wvalid && !s_axil_bvalid) begin
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// write operation
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s_axil_awready_next = 1'b1;
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s_axil_wready_next = 1'b1;
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s_axil_bvalid_next = 1'b1;
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case (s_axil_awaddr & {{AXIL_ADDR_WIDTH{1'b1}}, 2'b00})
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16'h0200: queue_enable_next = (queue_enable_reg & ~(32'hffffffff << 0)) | s_axil_wdata << 0;
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16'h0204: queue_enable_next = (queue_enable_reg & ~(32'hffffffff << 32)) | s_axil_wdata << 32;
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16'h0208: queue_enable_next = (queue_enable_reg & ~(32'hffffffff << 64)) | s_axil_wdata << 64;
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16'h020c: queue_enable_next = (queue_enable_reg & ~(32'hffffffff << 96)) | s_axil_wdata << 96;
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16'h0210: queue_enable_next = (queue_enable_reg & ~(32'hffffffff << 128)) | s_axil_wdata << 128;
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16'h0214: queue_enable_next = (queue_enable_reg & ~(32'hffffffff << 160)) | s_axil_wdata << 160;
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16'h0218: queue_enable_next = (queue_enable_reg & ~(32'hffffffff << 192)) | s_axil_wdata << 192;
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16'h021c: queue_enable_next = (queue_enable_reg & ~(32'hffffffff << 224)) | s_axil_wdata << 224;
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endcase
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end
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if (s_axil_arvalid && !s_axil_rvalid) begin
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// read operation
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s_axil_arready_next = 1'b1;
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s_axil_rvalid_next = 1'b1;
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s_axil_rdata_next = {AXIL_DATA_WIDTH{1'b0}};
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case (s_axil_araddr & {{AXIL_ADDR_WIDTH{1'b1}}, 2'b00})
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16'h0000: s_axil_rdata_next = 32'h00000001;
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16'h0010: s_axil_rdata_next = QUEUE_INDEX_WIDTH;
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16'h0014: s_axil_rdata_next = 0;
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//
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16'h0200: s_axil_rdata_next = queue_enable_reg;
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16'h0204: s_axil_rdata_next = queue_enable_reg >> 32;
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16'h0208: s_axil_rdata_next = queue_enable_reg >> 64;
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16'h020C: s_axil_rdata_next = queue_enable_reg >> 96;
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16'h0210: s_axil_rdata_next = queue_enable_reg >> 128;
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16'h0214: s_axil_rdata_next = queue_enable_reg >> 160;
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16'h0218: s_axil_rdata_next = queue_enable_reg >> 192;
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16'h021C: s_axil_rdata_next = queue_enable_reg >> 224;
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endcase
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end
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end
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always @(posedge clk) begin
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s_axil_awready_reg <= s_axil_awready_next;
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s_axil_wready_reg <= s_axil_wready_next;
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s_axil_bvalid_reg <= s_axil_bvalid_next;
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s_axil_arready_reg <= s_axil_arready_next;
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s_axil_rdata_reg <= s_axil_rdata_next;
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s_axil_rvalid_reg <= s_axil_rvalid_next;
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queue_enable_reg <= queue_enable_next;
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if (rst) begin
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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s_axil_bvalid_reg <= 1'b0;
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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queue_enable_reg <= 0;
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end
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end
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endmodule
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