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corundum/example/ExaNIC_X10/fpga/rtl
History
Alex Forencich d99afcb2f1 Change tag count
2019-07-13 11:21:19 -07:00
..
axi_ram.v
Add ExaNIC X10 example design
2019-07-13 11:06:29 -07:00
axis_register.v
Add ExaNIC X10 example design
2019-07-13 11:06:29 -07:00
debounce_switch.v
Add ExaNIC X10 example design
2019-07-13 11:06:29 -07:00
fpga_core.v
Change tag count
2019-07-13 11:21:19 -07:00
fpga.v
Add ExaNIC X10 example design
2019-07-13 11:06:29 -07:00
sync_reset.v
Add ExaNIC X10 example design
2019-07-13 11:06:29 -07:00
sync_signal.v
Add ExaNIC X10 example design
2019-07-13 11:06:29 -07:00