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675 lines
24 KiB
Verilog
675 lines
24 KiB
Verilog
/*
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Copyright 2021-2022, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* NIC Interface RX path
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*/
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module mqnic_interface_rx #
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(
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// Structural configuration
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parameter PORTS = 1,
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// PTP configuration
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parameter PTP_TS_WIDTH = 96,
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// Queue manager configuration (interface)
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parameter RX_QUEUE_INDEX_WIDTH = 8,
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parameter QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
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parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
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parameter CPL_QUEUE_INDEX_WIDTH = RX_CPL_QUEUE_INDEX_WIDTH,
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parameter QUEUE_PTR_WIDTH = 16,
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parameter LOG_QUEUE_SIZE_WIDTH = 4,
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parameter LOG_BLOCK_SIZE_WIDTH = 2,
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// Descriptor management
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parameter RX_MAX_DESC_REQ = 16,
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parameter RX_DESC_FIFO_SIZE = RX_MAX_DESC_REQ*8,
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parameter DESC_SIZE = 16,
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parameter CPL_SIZE = 32,
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parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
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parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
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parameter DESC_REQ_TAG_WIDTH = 8,
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parameter QUEUE_REQ_TAG_WIDTH = 8,
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parameter QUEUE_OP_TAG_WIDTH = 8,
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// TX and RX engine configuration
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parameter RX_DESC_TABLE_SIZE = 32,
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parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
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// Interface configuration
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parameter PTP_TS_ENABLE = 1,
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parameter RX_RSS_ENABLE = 1,
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parameter RX_HASH_ENABLE = 1,
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parameter RX_CHECKSUM_ENABLE = 1,
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parameter MAX_RX_SIZE = 9214,
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parameter RX_RAM_SIZE = 32768,
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// DMA interface configuration
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parameter DMA_ADDR_WIDTH = 64,
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parameter DMA_LEN_WIDTH = 16,
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parameter DMA_TAG_WIDTH = 16,
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parameter RAM_ADDR_WIDTH = $clog2(RX_RAM_SIZE),
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parameter RAM_SEG_COUNT = 2,
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parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT,
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parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
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parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
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parameter RAM_PIPELINE = 2,
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// Register interface configuration
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parameter REG_ADDR_WIDTH = 7,
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parameter REG_DATA_WIDTH = 32,
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parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
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parameter RB_BASE_ADDR = 0,
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parameter RB_NEXT_PTR = 0,
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// Streaming interface configuration
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parameter AXIS_DATA_WIDTH = 512*2**$clog2(PORTS),
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parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
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parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
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parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH,
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parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Control register interface
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*/
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input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
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input wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data,
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input wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
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input wire ctrl_reg_wr_en,
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output wire ctrl_reg_wr_wait,
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output wire ctrl_reg_wr_ack,
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input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
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input wire ctrl_reg_rd_en,
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output wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data,
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output wire ctrl_reg_rd_wait,
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output wire ctrl_reg_rd_ack,
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/*
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* Descriptor request output
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*/
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
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output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
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output wire m_axis_desc_req_valid,
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input wire m_axis_desc_req_ready,
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/*
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* Descriptor request status input
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*/
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input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
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input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
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input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
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input wire s_axis_desc_req_status_empty,
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input wire s_axis_desc_req_status_error,
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input wire s_axis_desc_req_status_valid,
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/*
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* Descriptor data input
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*/
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input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
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input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
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input wire s_axis_desc_tvalid,
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output wire s_axis_desc_tready,
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input wire s_axis_desc_tlast,
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
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input wire s_axis_desc_tuser,
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/*
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* Completion request output
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*/
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
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output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
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output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
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output wire m_axis_cpl_req_valid,
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input wire m_axis_cpl_req_ready,
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/*
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* Completion request status input
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*/
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
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input wire s_axis_cpl_req_status_full,
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input wire s_axis_cpl_req_status_error,
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input wire s_axis_cpl_req_status_valid,
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/*
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* DMA write descriptor output (data)
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*/
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output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
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output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
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output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
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output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
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output wire m_axis_dma_write_desc_valid,
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input wire m_axis_dma_write_desc_ready,
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/*
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* DMA write descriptor status input (data)
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*/
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input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
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input wire [3:0] s_axis_dma_write_desc_status_error,
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input wire s_axis_dma_write_desc_status_valid,
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/*
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* RAM interface (data)
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*/
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input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr,
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input wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_valid,
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output wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_ready,
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output wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data,
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output wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid,
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input wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready,
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/*
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* Receive data input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
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input wire s_axis_rx_tvalid,
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output wire s_axis_rx_tready,
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input wire s_axis_rx_tlast,
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input wire [AXIS_RX_ID_WIDTH-1:0] s_axis_rx_tid,
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input wire [AXIS_RX_DEST_WIDTH-1:0] s_axis_rx_tdest,
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input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
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/*
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* Configuration
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*/
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input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu
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);
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parameter DMA_CLIENT_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);
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parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;
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parameter REQ_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);
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localparam RX_HASH_WIDTH = 32;
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localparam RX_HASH_TYPE_WIDTH = 4;
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localparam TUSER_HASH_OFFSET = AXIS_RX_USER_WIDTH;
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localparam TUSER_HASH_TYPE_OFFSET = TUSER_HASH_OFFSET + (RX_HASH_ENABLE ? RX_HASH_WIDTH : 0);
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localparam INT_AXIS_RX_USER_WIDTH = TUSER_HASH_TYPE_OFFSET + (RX_HASH_ENABLE ? RX_HASH_TYPE_WIDTH : 0);
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wire [AXIS_DESC_DATA_WIDTH-1:0] rx_fifo_desc_tdata;
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wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_fifo_desc_tkeep;
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wire rx_fifo_desc_tvalid;
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wire rx_fifo_desc_tready;
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wire rx_fifo_desc_tlast;
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wire [DESC_REQ_TAG_WIDTH-1:0] rx_fifo_desc_tid;
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wire rx_fifo_desc_tuser;
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axis_fifo #(
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.DEPTH(RX_DESC_FIFO_SIZE*DESC_SIZE),
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.DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
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.KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
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.LAST_ENABLE(1),
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.ID_ENABLE(1),
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.ID_WIDTH(DESC_REQ_TAG_WIDTH),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.PIPELINE_OUTPUT(3),
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.FRAME_FIFO(0)
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)
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rx_desc_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(s_axis_desc_tdata),
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.s_axis_tkeep(s_axis_desc_tkeep),
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.s_axis_tvalid(s_axis_desc_tvalid),
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.s_axis_tready(s_axis_desc_tready),
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.s_axis_tlast(s_axis_desc_tlast),
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.s_axis_tid(s_axis_desc_tid),
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.s_axis_tdest(0),
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.s_axis_tuser(s_axis_desc_tuser),
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// AXI output
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.m_axis_tdata(rx_fifo_desc_tdata),
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.m_axis_tkeep(rx_fifo_desc_tkeep),
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.m_axis_tvalid(rx_fifo_desc_tvalid),
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.m_axis_tready(rx_fifo_desc_tready),
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.m_axis_tlast(rx_fifo_desc_tlast),
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.m_axis_tid(rx_fifo_desc_tid),
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.m_axis_tdest(),
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.m_axis_tuser(rx_fifo_desc_tuser),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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wire [15:0] rx_csum;
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wire rx_csum_valid;
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wire rx_csum_ready;
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wire [RAM_ADDR_WIDTH-1:0] dma_rx_desc_addr;
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wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_len;
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wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_tag;
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wire dma_rx_desc_valid;
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wire dma_rx_desc_ready;
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wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len;
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wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag;
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wire [AXIS_RX_ID_WIDTH-1:0] dma_rx_desc_status_id;
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wire [AXIS_RX_DEST_WIDTH-1:0] dma_rx_desc_status_dest;
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wire [INT_AXIS_RX_USER_WIDTH-1:0] dma_rx_desc_status_user;
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wire [3:0] dma_rx_desc_status_error;
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wire dma_rx_desc_status_valid;
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// Generate RX requests
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reg rx_frame_reg = 1'b0;
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reg [5:0] rx_req_cnt_reg = 0;
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wire rx_req_valid = rx_req_cnt_reg != 0;
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wire rx_req_ready;
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always @(posedge clk) begin
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if (rx_req_valid && rx_req_ready) begin
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rx_req_cnt_reg <= rx_req_cnt_reg - 1;
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end
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if (s_axis_rx_tvalid) begin
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if (!rx_frame_reg) begin
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if (rx_req_valid && rx_req_ready) begin
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rx_req_cnt_reg <= rx_req_cnt_reg;
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end else begin
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rx_req_cnt_reg <= rx_req_cnt_reg + 1;
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end
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rx_frame_reg <= 1'b1;
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end
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if (s_axis_rx_tready && s_axis_rx_tvalid && s_axis_rx_tlast) begin
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rx_frame_reg <= 1'b0;
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end
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end
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if (rst) begin
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rx_frame_reg <= 1'b0;
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rx_req_cnt_reg <= 0;
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end
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end
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rx_engine #(
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.PORTS(PORTS),
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.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
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.REG_DATA_WIDTH(REG_DATA_WIDTH),
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.REG_STRB_WIDTH(REG_STRB_WIDTH),
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.RB_BASE_ADDR(RB_BASE_ADDR),
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.RB_NEXT_PTR(RB_NEXT_PTR),
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.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
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.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
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.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
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.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
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.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
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.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
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.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
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.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
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.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
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.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
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.QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
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.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
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.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
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.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
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.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
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.MAX_RX_SIZE(MAX_RX_SIZE),
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.RX_BUFFER_OFFSET(0),
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.RX_BUFFER_SIZE(RX_RAM_SIZE),
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.RX_BUFFER_STEP_SIZE(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
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.DESC_SIZE(DESC_SIZE),
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.CPL_SIZE(CPL_SIZE),
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.MAX_DESC_REQ(RX_MAX_DESC_REQ),
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.AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
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.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
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.PTP_TS_ENABLE(PTP_TS_ENABLE),
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.PTP_TS_WIDTH(PTP_TS_WIDTH),
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.RX_HASH_ENABLE(RX_HASH_ENABLE),
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.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
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.AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH),
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.AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
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.AXIS_RX_USER_WIDTH(INT_AXIS_RX_USER_WIDTH)
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)
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rx_engine_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Control register interface
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*/
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.ctrl_reg_wr_addr(ctrl_reg_wr_addr),
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.ctrl_reg_wr_data(ctrl_reg_wr_data),
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.ctrl_reg_wr_strb(ctrl_reg_wr_strb),
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.ctrl_reg_wr_en(ctrl_reg_wr_en),
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.ctrl_reg_wr_wait(ctrl_reg_wr_wait),
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.ctrl_reg_wr_ack(ctrl_reg_wr_ack),
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.ctrl_reg_rd_addr(ctrl_reg_rd_addr),
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.ctrl_reg_rd_en(ctrl_reg_rd_en),
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.ctrl_reg_rd_data(ctrl_reg_rd_data),
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.ctrl_reg_rd_wait(ctrl_reg_rd_wait),
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.ctrl_reg_rd_ack(ctrl_reg_rd_ack),
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/*
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* Receive request input (queue index)
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*/
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.s_axis_rx_req_tag(0),
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.s_axis_rx_req_valid(rx_req_valid),
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.s_axis_rx_req_ready(rx_req_ready),
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/*
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* Receive request status output
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*/
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.m_axis_rx_req_status_tag(),
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.m_axis_rx_req_status_len(),
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.m_axis_rx_req_status_valid(),
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/*
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* Descriptor request output
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*/
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.m_axis_desc_req_queue(m_axis_desc_req_queue),
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.m_axis_desc_req_tag(m_axis_desc_req_tag),
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.m_axis_desc_req_valid(m_axis_desc_req_valid),
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.m_axis_desc_req_ready(m_axis_desc_req_ready),
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/*
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* Descriptor request status input
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*/
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.s_axis_desc_req_status_queue(s_axis_desc_req_status_queue),
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.s_axis_desc_req_status_ptr(s_axis_desc_req_status_ptr),
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.s_axis_desc_req_status_cpl(s_axis_desc_req_status_cpl),
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.s_axis_desc_req_status_tag(s_axis_desc_req_status_tag),
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.s_axis_desc_req_status_empty(s_axis_desc_req_status_empty),
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.s_axis_desc_req_status_error(s_axis_desc_req_status_error),
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.s_axis_desc_req_status_valid(s_axis_desc_req_status_valid),
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/*
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* Descriptor data input
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*/
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.s_axis_desc_tdata(rx_fifo_desc_tdata),
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.s_axis_desc_tkeep(rx_fifo_desc_tkeep),
|
|
.s_axis_desc_tvalid(rx_fifo_desc_tvalid),
|
|
.s_axis_desc_tready(rx_fifo_desc_tready),
|
|
.s_axis_desc_tlast(rx_fifo_desc_tlast),
|
|
.s_axis_desc_tid(rx_fifo_desc_tid),
|
|
.s_axis_desc_tuser(rx_fifo_desc_tuser),
|
|
|
|
/*
|
|
* Completion request output
|
|
*/
|
|
.m_axis_cpl_req_queue(m_axis_cpl_req_queue),
|
|
.m_axis_cpl_req_tag(m_axis_cpl_req_tag),
|
|
.m_axis_cpl_req_data(m_axis_cpl_req_data),
|
|
.m_axis_cpl_req_valid(m_axis_cpl_req_valid),
|
|
.m_axis_cpl_req_ready(m_axis_cpl_req_ready),
|
|
|
|
/*
|
|
* Completion request status input
|
|
*/
|
|
.s_axis_cpl_req_status_tag(s_axis_cpl_req_status_tag),
|
|
.s_axis_cpl_req_status_full(s_axis_cpl_req_status_full),
|
|
.s_axis_cpl_req_status_error(s_axis_cpl_req_status_error),
|
|
.s_axis_cpl_req_status_valid(s_axis_cpl_req_status_valid),
|
|
|
|
/*
|
|
* DMA write descriptor output
|
|
*/
|
|
.m_axis_dma_write_desc_dma_addr(m_axis_dma_write_desc_dma_addr),
|
|
.m_axis_dma_write_desc_ram_addr(m_axis_dma_write_desc_ram_addr),
|
|
.m_axis_dma_write_desc_len(m_axis_dma_write_desc_len),
|
|
.m_axis_dma_write_desc_tag(m_axis_dma_write_desc_tag),
|
|
.m_axis_dma_write_desc_valid(m_axis_dma_write_desc_valid),
|
|
.m_axis_dma_write_desc_ready(m_axis_dma_write_desc_ready),
|
|
|
|
/*
|
|
* DMA write descriptor status input
|
|
*/
|
|
.s_axis_dma_write_desc_status_tag(s_axis_dma_write_desc_status_tag),
|
|
.s_axis_dma_write_desc_status_error(s_axis_dma_write_desc_status_error),
|
|
.s_axis_dma_write_desc_status_valid(s_axis_dma_write_desc_status_valid),
|
|
|
|
/*
|
|
* Receive descriptor output
|
|
*/
|
|
.m_axis_rx_desc_addr(dma_rx_desc_addr),
|
|
.m_axis_rx_desc_len(dma_rx_desc_len),
|
|
.m_axis_rx_desc_tag(dma_rx_desc_tag),
|
|
.m_axis_rx_desc_valid(dma_rx_desc_valid),
|
|
.m_axis_rx_desc_ready(dma_rx_desc_ready),
|
|
|
|
/*
|
|
* Receive descriptor status input
|
|
*/
|
|
.s_axis_rx_desc_status_len(dma_rx_desc_status_len),
|
|
.s_axis_rx_desc_status_tag(dma_rx_desc_status_tag),
|
|
.s_axis_rx_desc_status_id(dma_rx_desc_status_id),
|
|
.s_axis_rx_desc_status_dest(dma_rx_desc_status_dest),
|
|
.s_axis_rx_desc_status_user(dma_rx_desc_status_user),
|
|
.s_axis_rx_desc_status_error(dma_rx_desc_status_error),
|
|
.s_axis_rx_desc_status_valid(dma_rx_desc_status_valid),
|
|
|
|
/*
|
|
* Receive checksum input
|
|
*/
|
|
.s_axis_rx_csum(rx_csum),
|
|
.s_axis_rx_csum_valid(rx_csum_valid),
|
|
.s_axis_rx_csum_ready(rx_csum_ready),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.mtu(mtu),
|
|
.enable(1'b1)
|
|
);
|
|
|
|
wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int;
|
|
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int;
|
|
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int;
|
|
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int;
|
|
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int;
|
|
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_done_int;
|
|
|
|
dma_psdpram #(
|
|
.SIZE(RX_RAM_SIZE),
|
|
.SEG_COUNT(RAM_SEG_COUNT),
|
|
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
|
|
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
|
|
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
|
|
.PIPELINE(RAM_PIPELINE)
|
|
)
|
|
dma_psdpram_rx_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Write port
|
|
*/
|
|
.wr_cmd_be(dma_ram_wr_cmd_be_int),
|
|
.wr_cmd_addr(dma_ram_wr_cmd_addr_int),
|
|
.wr_cmd_data(dma_ram_wr_cmd_data_int),
|
|
.wr_cmd_valid(dma_ram_wr_cmd_valid_int),
|
|
.wr_cmd_ready(dma_ram_wr_cmd_ready_int),
|
|
.wr_done(dma_ram_wr_done_int),
|
|
|
|
/*
|
|
* Read port
|
|
*/
|
|
.rd_cmd_addr(dma_ram_rd_cmd_addr),
|
|
.rd_cmd_valid(dma_ram_rd_cmd_valid),
|
|
.rd_cmd_ready(dma_ram_rd_cmd_ready),
|
|
.rd_resp_data(dma_ram_rd_resp_data),
|
|
.rd_resp_valid(dma_ram_rd_resp_valid),
|
|
.rd_resp_ready(dma_ram_rd_resp_ready)
|
|
);
|
|
|
|
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_int;
|
|
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_int;
|
|
wire rx_axis_tvalid_int;
|
|
wire rx_axis_tready_int;
|
|
wire rx_axis_tlast_int;
|
|
wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid_int;
|
|
wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest_int;
|
|
wire [INT_AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser_int;
|
|
|
|
mqnic_ingress #(
|
|
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
|
|
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
|
|
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
|
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
|
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
|
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.AXIS_ID_WIDTH(AXIS_RX_ID_WIDTH),
|
|
.AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
|
|
.S_AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH),
|
|
.M_AXIS_USER_WIDTH(INT_AXIS_RX_USER_WIDTH),
|
|
.MAX_RX_SIZE(MAX_RX_SIZE)
|
|
)
|
|
ingress_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Receive data input
|
|
*/
|
|
.s_axis_tdata(s_axis_rx_tdata),
|
|
.s_axis_tkeep(s_axis_rx_tkeep),
|
|
.s_axis_tvalid(s_axis_rx_tvalid),
|
|
.s_axis_tready(s_axis_rx_tready),
|
|
.s_axis_tlast(s_axis_rx_tlast),
|
|
.s_axis_tid(s_axis_rx_tid),
|
|
.s_axis_tdest(s_axis_rx_tdest),
|
|
.s_axis_tuser(s_axis_rx_tuser),
|
|
|
|
/*
|
|
* Receive data output
|
|
*/
|
|
.m_axis_tdata(rx_axis_tdata_int),
|
|
.m_axis_tkeep(rx_axis_tkeep_int),
|
|
.m_axis_tvalid(rx_axis_tvalid_int),
|
|
.m_axis_tready(rx_axis_tready_int),
|
|
.m_axis_tlast(rx_axis_tlast_int),
|
|
.m_axis_tid(rx_axis_tid_int),
|
|
.m_axis_tdest(rx_axis_tdest_int),
|
|
.m_axis_tuser(rx_axis_tuser_int),
|
|
|
|
/*
|
|
* RX checksum output
|
|
*/
|
|
.rx_csum(rx_csum),
|
|
.rx_csum_valid(rx_csum_valid),
|
|
.rx_csum_ready(rx_csum_ready)
|
|
);
|
|
|
|
dma_client_axis_sink #(
|
|
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
|
|
.SEG_COUNT(RAM_SEG_COUNT),
|
|
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
|
|
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
|
|
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
|
|
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
|
|
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.AXIS_LAST_ENABLE(1),
|
|
.AXIS_ID_ENABLE(1),
|
|
.AXIS_ID_WIDTH(AXIS_RX_ID_WIDTH),
|
|
.AXIS_DEST_ENABLE(1),
|
|
.AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
|
|
.AXIS_USER_ENABLE(1),
|
|
.AXIS_USER_WIDTH(INT_AXIS_RX_USER_WIDTH),
|
|
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
|
|
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
|
|
)
|
|
dma_client_axis_sink_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* DMA write descriptor input
|
|
*/
|
|
.s_axis_write_desc_ram_addr(dma_rx_desc_addr),
|
|
.s_axis_write_desc_len(dma_rx_desc_len),
|
|
.s_axis_write_desc_tag(dma_rx_desc_tag),
|
|
.s_axis_write_desc_valid(dma_rx_desc_valid),
|
|
.s_axis_write_desc_ready(dma_rx_desc_ready),
|
|
|
|
/*
|
|
* DMA write descriptor status output
|
|
*/
|
|
.m_axis_write_desc_status_len(dma_rx_desc_status_len),
|
|
.m_axis_write_desc_status_tag(dma_rx_desc_status_tag),
|
|
.m_axis_write_desc_status_id(dma_rx_desc_status_id),
|
|
.m_axis_write_desc_status_dest(dma_rx_desc_status_dest),
|
|
.m_axis_write_desc_status_user(dma_rx_desc_status_user),
|
|
.m_axis_write_desc_status_error(dma_rx_desc_status_error),
|
|
.m_axis_write_desc_status_valid(dma_rx_desc_status_valid),
|
|
|
|
/*
|
|
* AXI stream write data input
|
|
*/
|
|
.s_axis_write_data_tdata(rx_axis_tdata_int),
|
|
.s_axis_write_data_tkeep(rx_axis_tkeep_int),
|
|
.s_axis_write_data_tvalid(rx_axis_tvalid_int),
|
|
.s_axis_write_data_tready(rx_axis_tready_int),
|
|
.s_axis_write_data_tlast(rx_axis_tlast_int),
|
|
.s_axis_write_data_tid(rx_axis_tid_int),
|
|
.s_axis_write_data_tdest(rx_axis_tdest_int),
|
|
.s_axis_write_data_tuser(rx_axis_tuser_int),
|
|
|
|
/*
|
|
* RAM interface
|
|
*/
|
|
.ram_wr_cmd_be(dma_ram_wr_cmd_be_int),
|
|
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr_int),
|
|
.ram_wr_cmd_data(dma_ram_wr_cmd_data_int),
|
|
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid_int),
|
|
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready_int),
|
|
.ram_wr_done(dma_ram_wr_done_int),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.enable(1'b1),
|
|
.abort(1'b0)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|