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257 lines
7.0 KiB
Verilog
257 lines
7.0 KiB
Verilog
/*
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Copyright (c) 2015-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 1G Ethernet MAC with RGMII interface
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*/
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module eth_mac_1g_rgmii #
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(
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// target ("SIM", "GENERIC", "XILINX", "ALTERA")
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parameter TARGET = "GENERIC",
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// IODDR style ("IODDR", "IODDR2")
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// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
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// Use IODDR2 for Spartan-6
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parameter IODDR_STYLE = "IODDR2",
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// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
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// Use BUFR for Virtex-6, 7-series
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// Use BUFG for Virtex-5, Spartan-6, Ultrascale
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parameter CLOCK_INPUT_STYLE = "BUFG",
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// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
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parameter USE_CLK90 = "TRUE",
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parameter ENABLE_PADDING = 1,
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parameter MIN_FRAME_LENGTH = 64
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)
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(
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input wire gtx_clk,
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input wire gtx_clk90,
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input wire gtx_rst,
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output wire rx_clk,
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output wire rx_rst,
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output wire tx_clk,
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output wire tx_rst,
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/*
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* AXI input
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*/
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input wire [7:0] tx_axis_tdata,
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input wire tx_axis_tvalid,
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output wire tx_axis_tready,
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input wire tx_axis_tlast,
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input wire tx_axis_tuser,
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/*
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* AXI output
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*/
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output wire [7:0] rx_axis_tdata,
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output wire rx_axis_tvalid,
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output wire rx_axis_tlast,
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output wire rx_axis_tuser,
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/*
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* RGMII interface
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*/
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input wire rgmii_rx_clk,
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input wire [3:0] rgmii_rxd,
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input wire rgmii_rx_ctl,
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output wire rgmii_tx_clk,
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output wire [3:0] rgmii_txd,
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output wire rgmii_tx_ctl,
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/*
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* Status
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*/
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output wire tx_error_underflow,
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output wire rx_error_bad_frame,
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output wire rx_error_bad_fcs,
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output wire [1:0] speed,
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/*
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* Configuration
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*/
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input wire [7:0] cfg_ifg,
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input wire cfg_tx_enable,
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input wire cfg_rx_enable
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);
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wire [7:0] mac_gmii_rxd;
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wire mac_gmii_rx_dv;
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wire mac_gmii_rx_er;
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wire mac_gmii_tx_clk_en;
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wire [7:0] mac_gmii_txd;
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wire mac_gmii_tx_en;
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wire mac_gmii_tx_er;
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reg [1:0] speed_reg = 2'b10;
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reg mii_select_reg = 1'b0;
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(* srl_style = "register" *)
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reg [1:0] tx_mii_select_sync = 2'd0;
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always @(posedge tx_clk) begin
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tx_mii_select_sync <= {tx_mii_select_sync[0], mii_select_reg};
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end
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(* srl_style = "register" *)
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reg [1:0] rx_mii_select_sync = 2'd0;
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always @(posedge rx_clk) begin
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rx_mii_select_sync <= {rx_mii_select_sync[0], mii_select_reg};
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end
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// PHY speed detection
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reg [2:0] rx_prescale = 3'd0;
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always @(posedge rx_clk) begin
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rx_prescale <= rx_prescale + 3'd1;
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end
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(* srl_style = "register" *)
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reg [2:0] rx_prescale_sync = 3'd0;
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always @(posedge gtx_clk) begin
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rx_prescale_sync <= {rx_prescale_sync[1:0], rx_prescale[2]};
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end
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reg [6:0] rx_speed_count_1 = 0;
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reg [1:0] rx_speed_count_2 = 0;
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always @(posedge gtx_clk) begin
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if (gtx_rst) begin
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rx_speed_count_1 <= 0;
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rx_speed_count_2 <= 0;
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speed_reg <= 2'b10;
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mii_select_reg <= 1'b0;
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end else begin
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rx_speed_count_1 <= rx_speed_count_1 + 1;
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if (rx_prescale_sync[1] ^ rx_prescale_sync[2]) begin
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rx_speed_count_2 <= rx_speed_count_2 + 1;
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end
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if (&rx_speed_count_1) begin
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// reference count overflow - 10M
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rx_speed_count_1 <= 0;
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rx_speed_count_2 <= 0;
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speed_reg <= 2'b00;
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mii_select_reg <= 1'b1;
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end
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if (&rx_speed_count_2) begin
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// prescaled count overflow - 100M or 1000M
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rx_speed_count_1 <= 0;
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rx_speed_count_2 <= 0;
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if (rx_speed_count_1[6:5]) begin
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// large reference count - 100M
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speed_reg <= 2'b01;
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mii_select_reg <= 1'b1;
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end else begin
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// small reference count - 1000M
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speed_reg <= 2'b10;
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mii_select_reg <= 1'b0;
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end
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end
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end
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end
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assign speed = speed_reg;
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rgmii_phy_if #(
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.TARGET(TARGET),
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.IODDR_STYLE(IODDR_STYLE),
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.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
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.USE_CLK90(USE_CLK90)
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)
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rgmii_phy_if_inst (
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.clk(gtx_clk),
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.clk90(gtx_clk90),
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.rst(gtx_rst),
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.mac_gmii_rx_clk(rx_clk),
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.mac_gmii_rx_rst(rx_rst),
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.mac_gmii_rxd(mac_gmii_rxd),
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.mac_gmii_rx_dv(mac_gmii_rx_dv),
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.mac_gmii_rx_er(mac_gmii_rx_er),
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.mac_gmii_tx_clk(tx_clk),
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.mac_gmii_tx_rst(tx_rst),
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.mac_gmii_tx_clk_en(mac_gmii_tx_clk_en),
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.mac_gmii_txd(mac_gmii_txd),
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.mac_gmii_tx_en(mac_gmii_tx_en),
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.mac_gmii_tx_er(mac_gmii_tx_er),
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.phy_rgmii_rx_clk(rgmii_rx_clk),
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.phy_rgmii_rxd(rgmii_rxd),
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.phy_rgmii_rx_ctl(rgmii_rx_ctl),
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.phy_rgmii_tx_clk(rgmii_tx_clk),
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.phy_rgmii_txd(rgmii_txd),
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.phy_rgmii_tx_ctl(rgmii_tx_ctl),
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.speed(speed)
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);
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eth_mac_1g #(
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.ENABLE_PADDING(ENABLE_PADDING),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
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)
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eth_mac_1g_inst (
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.tx_clk(tx_clk),
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.tx_rst(tx_rst),
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.rx_clk(rx_clk),
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.rx_rst(rx_rst),
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.tx_axis_tdata(tx_axis_tdata),
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.tx_axis_tvalid(tx_axis_tvalid),
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.tx_axis_tready(tx_axis_tready),
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.tx_axis_tlast(tx_axis_tlast),
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.tx_axis_tuser(tx_axis_tuser),
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.rx_axis_tdata(rx_axis_tdata),
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.rx_axis_tvalid(rx_axis_tvalid),
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.rx_axis_tlast(rx_axis_tlast),
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.rx_axis_tuser(rx_axis_tuser),
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.gmii_rxd(mac_gmii_rxd),
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.gmii_rx_dv(mac_gmii_rx_dv),
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.gmii_rx_er(mac_gmii_rx_er),
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.gmii_txd(mac_gmii_txd),
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.gmii_tx_en(mac_gmii_tx_en),
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.gmii_tx_er(mac_gmii_tx_er),
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.rx_clk_enable(1'b1),
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.tx_clk_enable(mac_gmii_tx_clk_en),
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.rx_mii_select(rx_mii_select_sync[1]),
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.tx_mii_select(tx_mii_select_sync[1]),
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.tx_error_underflow(tx_error_underflow),
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.rx_error_bad_frame(rx_error_bad_frame),
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.rx_error_bad_fcs(rx_error_bad_fcs),
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.cfg_ifg(cfg_ifg),
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.cfg_tx_enable(cfg_tx_enable),
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.cfg_rx_enable(cfg_rx_enable)
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);
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endmodule
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`resetall
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