mirror of
https://github.com/corundum/corundum.git
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389 lines
13 KiB
Python
Executable File
389 lines
13 KiB
Python
Executable File
#!/usr/bin/env python
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"""eth_mux_64
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Generates an Ethernet mux with the specified number of ports
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Usage: eth_mux_64 [OPTION]...
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-?, --help display this help and exit
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-p, --ports specify number of ports
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-n, --name specify module name
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-o, --output specify output file name
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"""
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import io
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import sys
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import getopt
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from math import *
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from jinja2 import Template
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class Usage(Exception):
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def __init__(self, msg):
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self.msg = msg
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def main(argv=None):
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if argv is None:
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argv = sys.argv
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try:
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try:
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opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
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except getopt.error as msg:
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raise Usage(msg)
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# more code, unchanged
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except Usage as err:
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print(err.msg, file=sys.stderr)
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print("for help use --help", file=sys.stderr)
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return 2
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ports = 4
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name = None
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out_name = None
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# process options
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for o, a in opts:
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if o in ('-?', '--help'):
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print(__doc__)
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sys.exit(0)
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if o in ('-p', '--ports'):
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ports = int(a)
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if o in ('-n', '--name'):
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name = a
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if o in ('-o', '--output'):
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out_name = a
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if name is None:
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name = "eth_mux_64_{0}".format(ports)
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if out_name is None:
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out_name = name + ".v"
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print("Opening file '%s'..." % out_name)
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try:
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out_file = open(out_name, 'w')
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except Exception as ex:
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print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
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exit(1)
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print("Generating {0} port Ethernet mux {1}...".format(ports, name))
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select_width = ceil(log2(ports))
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t = Template(u"""/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ethernet {{n}} port multiplexer (64 bit datapath)
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*/
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module {{name}}
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame inputs
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*/
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{%- for p in ports %}
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input wire input_{{p}}_eth_hdr_valid,
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output wire input_{{p}}_eth_hdr_ready,
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input wire [47:0] input_{{p}}_eth_dest_mac,
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input wire [47:0] input_{{p}}_eth_src_mac,
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input wire [15:0] input_{{p}}_eth_type,
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input wire [63:0] input_{{p}}_eth_payload_tdata,
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input wire [7:0] input_{{p}}_eth_payload_tkeep,
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input wire input_{{p}}_eth_payload_tvalid,
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output wire input_{{p}}_eth_payload_tready,
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input wire input_{{p}}_eth_payload_tlast,
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input wire input_{{p}}_eth_payload_tuser,
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{% endfor %}
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/*
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* Ethernet frame output
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*/
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output wire output_eth_hdr_valid,
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input wire output_eth_hdr_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [63:0] output_eth_payload_tdata,
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output wire [7:0] output_eth_payload_tkeep,
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output wire output_eth_payload_tvalid,
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input wire output_eth_payload_tready,
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output wire output_eth_payload_tlast,
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output wire output_eth_payload_tuser,
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/*
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* Control
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*/
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input wire enable,
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input wire [{{w-1}}:0] select
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);
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reg [{{w-1}}:0] select_reg = 0, select_next;
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reg frame_reg = 0, frame_next;
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{% for p in ports %}
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reg input_{{p}}_eth_hdr_ready_reg = 0, input_{{p}}_eth_hdr_ready_next;
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{%- endfor %}
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{% for p in ports %}
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reg input_{{p}}_eth_payload_tready_reg = 0, input_{{p}}_eth_payload_tready_next;
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{%- endfor %}
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reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next;
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reg [47:0] output_eth_dest_mac_reg = 0, output_eth_dest_mac_next;
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reg [47:0] output_eth_src_mac_reg = 0, output_eth_src_mac_next;
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reg [15:0] output_eth_type_reg = 0, output_eth_type_next;
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// internal datapath
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reg [63:0] output_eth_payload_tdata_int;
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reg [7:0] output_eth_payload_tkeep_int;
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reg output_eth_payload_tvalid_int;
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reg output_eth_payload_tready_int = 0;
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reg output_eth_payload_tlast_int;
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reg output_eth_payload_tuser_int;
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wire output_eth_payload_tready_int_early;
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{% for p in ports %}
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assign input_{{p}}_eth_hdr_ready = input_{{p}}_eth_hdr_ready_reg;
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{%- endfor %}
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{% for p in ports %}
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assign input_{{p}}_eth_payload_tready = input_{{p}}_eth_payload_tready_reg;
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{%- endfor %}
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assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
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assign output_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_eth_src_mac = output_eth_src_mac_reg;
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assign output_eth_type = output_eth_type_reg;
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// mux for start of packet detection
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reg selected_input_eth_hdr_valid;
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reg [47:0] selected_input_eth_dest_mac;
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reg [47:0] selected_input_eth_src_mac;
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reg [15:0] selected_input_eth_type;
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always @* begin
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case (select)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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selected_input_eth_hdr_valid = input_{{p}}_eth_hdr_valid;
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selected_input_eth_dest_mac = input_{{p}}_eth_dest_mac;
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selected_input_eth_src_mac = input_{{p}}_eth_src_mac;
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selected_input_eth_type = input_{{p}}_eth_type;
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end
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{%- endfor %}
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endcase
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end
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// mux for incoming packet
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reg [63:0] current_input_tdata;
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reg [7:0] current_input_tkeep;
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reg current_input_tvalid;
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reg current_input_tready;
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reg current_input_tlast;
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reg current_input_tuser;
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always @* begin
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case (select_reg)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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current_input_tdata = input_{{p}}_eth_payload_tdata;
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current_input_tkeep = input_{{p}}_eth_payload_tkeep;
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current_input_tvalid = input_{{p}}_eth_payload_tvalid;
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current_input_tready = input_{{p}}_eth_payload_tready;
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current_input_tlast = input_{{p}}_eth_payload_tlast;
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current_input_tuser = input_{{p}}_eth_payload_tuser;
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end
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{%- endfor %}
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endcase
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end
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always @* begin
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select_next = select_reg;
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frame_next = frame_reg;
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{% for p in ports %}
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input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_reg & ~input_{{p}}_eth_hdr_valid;
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{%- endfor %}
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{% for p in ports %}
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input_{{p}}_eth_payload_tready_next = 0;
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{%- endfor %}
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output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
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output_eth_dest_mac_next = output_eth_dest_mac_reg;
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output_eth_src_mac_next = output_eth_src_mac_reg;
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output_eth_type_next = output_eth_type_reg;
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if (frame_reg) begin
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if (current_input_tvalid & current_input_tready) begin
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// end of frame detection
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frame_next = ~current_input_tlast;
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end
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end else if (enable & ~output_eth_hdr_valid & selected_input_eth_hdr_valid) begin
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// start of frame, grab select value
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frame_next = 1;
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select_next = select;
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case (select_next)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_eth_hdr_ready_next = 1;
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{%- endfor %}
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endcase
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output_eth_hdr_valid_next = 1;
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output_eth_dest_mac_next = selected_input_eth_dest_mac;
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output_eth_src_mac_next = selected_input_eth_src_mac;
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output_eth_type_next = selected_input_eth_type;
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end
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// generate ready signal on selected port
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case (select_next)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
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{%- endfor %}
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endcase
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// pass through selected packet data
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output_eth_payload_tdata_int = current_input_tdata;
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output_eth_payload_tkeep_int = current_input_tkeep;
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output_eth_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
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output_eth_payload_tlast_int = current_input_tlast;
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output_eth_payload_tuser_int = current_input_tuser;
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end
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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select_reg <= 0;
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frame_reg <= 0;
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{%- for p in ports %}
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input_{{p}}_eth_hdr_ready_reg <= 0;
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{%- endfor %}
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{%- for p in ports %}
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input_{{p}}_eth_payload_tready_reg <= 0;
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{%- endfor %}
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output_eth_hdr_valid_reg <= 0;
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output_eth_dest_mac_reg <= 0;
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output_eth_src_mac_reg <= 0;
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output_eth_type_reg <= 0;
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end else begin
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select_reg <= select_next;
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frame_reg <= frame_next;
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{%- for p in ports %}
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input_{{p}}_eth_hdr_ready_reg <= input_{{p}}_eth_hdr_ready_next;
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{%- endfor %}
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{%- for p in ports %}
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input_{{p}}_eth_payload_tready_reg <= input_{{p}}_eth_payload_tready_next;
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{%- endfor %}
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output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
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output_eth_dest_mac_reg <= output_eth_dest_mac_next;
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output_eth_src_mac_reg <= output_eth_src_mac_next;
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output_eth_type_reg <= output_eth_type_next;
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end
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end
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// output datapath logic
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reg [63:0] output_eth_payload_tdata_reg = 0;
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reg [7:0] output_eth_payload_tkeep_reg = 0;
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reg output_eth_payload_tvalid_reg = 0;
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reg output_eth_payload_tlast_reg = 0;
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reg output_eth_payload_tuser_reg = 0;
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reg [63:0] temp_eth_payload_tdata_reg = 0;
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reg [7:0] temp_eth_payload_tkeep_reg = 0;
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reg temp_eth_payload_tvalid_reg = 0;
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reg temp_eth_payload_tlast_reg = 0;
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reg temp_eth_payload_tuser_reg = 0;
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assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
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assign output_eth_payload_tkeep = output_eth_payload_tkeep_reg;
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assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
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assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
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assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
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// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
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assign output_eth_payload_tready_int_early = output_eth_payload_tready | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_reg) | (~temp_eth_payload_tvalid_reg & ~output_eth_payload_tvalid_int);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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output_eth_payload_tdata_reg <= 0;
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output_eth_payload_tkeep_reg <= 0;
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output_eth_payload_tvalid_reg <= 0;
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output_eth_payload_tlast_reg <= 0;
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output_eth_payload_tuser_reg <= 0;
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output_eth_payload_tready_int <= 0;
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temp_eth_payload_tdata_reg <= 0;
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temp_eth_payload_tkeep_reg <= 0;
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temp_eth_payload_tvalid_reg <= 0;
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temp_eth_payload_tlast_reg <= 0;
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temp_eth_payload_tuser_reg <= 0;
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end else begin
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// transfer sink ready state to source
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output_eth_payload_tready_int <= output_eth_payload_tready_int_early;
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if (output_eth_payload_tready_int) begin
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// input is ready
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if (output_eth_payload_tready | ~output_eth_payload_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
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output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
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output_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int;
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output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
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output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
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end else begin
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// output is not ready, store input in temp
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temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
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temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
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temp_eth_payload_tvalid_reg <= output_eth_payload_tvalid_int;
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temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
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temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
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end
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end else if (output_eth_payload_tready) begin
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// input is not ready, but output is ready
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output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
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output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg;
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output_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_reg;
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output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
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output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
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temp_eth_payload_tdata_reg <= 0;
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temp_eth_payload_tkeep_reg <= 0;
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temp_eth_payload_tvalid_reg <= 0;
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temp_eth_payload_tlast_reg <= 0;
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temp_eth_payload_tuser_reg <= 0;
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end
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end
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end
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endmodule
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""")
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out_file.write(t.render(
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n=ports,
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w=select_width,
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name=name,
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ports=range(ports)
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))
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print("Done")
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if __name__ == "__main__":
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sys.exit(main())
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