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142 lines
3.9 KiB
Makefile
142 lines
3.9 KiB
Makefile
###################################################################
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#
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# Altera FPGA Makefile
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#
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# Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. Stratix V)
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# FPGA_DEVICE - FPGA device (e.g. 5SGXEA7N2F45C2)
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# SYN_FILES - space-separated list of source files
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# QSF_FILES - space-separated list of settings files
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# SDC_FILES - space-separated list of timing constraint files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = "Stratix V"
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# FPGA_DEVICE = 5SGXEA7N2F45C2
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# SYN_FILES = rtl/fpga.v rtl/clocks.v
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# QSF_FILES = fpga.qsf
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# SDC_FILES = fpga.sdc
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# include ../common/altera.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# output files to hang on to
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.PRECIOUS: %.sof %.map.rpt %.fit.rpt %.asm.rpt %.sta.rpt
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# any project specific settings
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-include ../config.mk
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SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
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ifdef QSF_FILES
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QSF_FILES_REL = $(patsubst %, ../%, $(QSF_FILES))
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else
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QSF_FILES_REL = ../$(FPGA_TOP).qsf
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endif
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SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES))
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ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and database
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).sof
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clean:
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rm -rf *.rpt *.summary *.smsg *.chg smart.log *.htm *.eqn *.pin *.sof *.pof *.qsf *.qpf *.jdi *.sld *.txt db incremental_db reconfig_mif
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map: smart.log $(PROJECT).map.rpt
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fit: smart.log $(PROJECT).fit.rpt
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asm: smart.log $(PROJECT).asm.rpt
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sta: smart.log $(PROJECT).sta.rpt
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smart: smart.log
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###################################################################
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# Executable Configuration
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###################################################################
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MAP_ARGS = --family=$(FPGA_FAMILY)
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FIT_ARGS = --part=$(FPGA_DEVICE)
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ASM_ARGS =
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STA_ARGS =
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###################################################################
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# Target implementations
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###################################################################
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STAMP = echo done >
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%.map.rpt: map.chg $(SYN_FILES_REL)
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quartus_map $(MAP_ARGS) $(FPGA_TOP)
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%.fit.rpt: fit.chg %.map.rpt
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quartus_fit $(FIT_ARGS) $(FPGA_TOP)
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%.sta.rpt: sta.chg %.fit.rpt
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quartus_sta $(STA_ARGS) $(FPGA_TOP)
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%.asm.rpt: asm.chg %.sta.rpt
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quartus_asm $(ASM_ARGS) $(FPGA_TOP)
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mkdir -p rev
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EXT=sof; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do let COUNT=COUNT+1; done; \
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cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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%.sof: smart.log %.asm.rpt
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smart.log: $(ASSIGNMENT_FILES)
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quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log
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###################################################################
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# Project initialization
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###################################################################
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$(ASSIGNMENT_FILES): $(QSF_FILES_REL) $(SYN_FILES_REL)
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rm -f $(FPGA_TOP).qsf
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quartus_sh --prepare -f $(FPGA_FAMILY) -d $(FPGA_DEVICE) -t $(FPGA_TOP) $(FPGA_TOP)
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echo >> $(FPGA_TOP).qsf
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echo >> $(FPGA_TOP).qsf
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echo "# Source files" >> $(FPGA_TOP).qsf
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for x in $(SYN_FILES_REL); do \
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case $${x##*.} in \
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v|V) echo set_global_assignment -name VERILOG_FILE $$x >> $(FPGA_TOP).qsf ;;\
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vhd|VHD) echo set_global_assignment -name VHDL_FILE $$x >> $(FPGA_TOP).qsf ;;\
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qip|QIP) echo set_global_assignment -name QIP_FILE $$x >> $(FPGA_TOP).qsf ;;\
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*) echo set_global_assignment -name SOURCE_FILE $$x >> $(FPGA_TOP).qsf ;;\
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esac; \
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done
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echo >> $(FPGA_TOP).qsf
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echo "# SDC files" >> $(FPGA_TOP).qsf
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for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE $$x >> $(FPGA_TOP).qsf; done
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for x in $(QSF_FILES_REL); do printf "\n#\n# Included QSF file $$x\n#\n" >> $(FPGA_TOP).qsf; cat $$x >> $(FPGA_TOP).qsf; done
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map.chg:
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$(STAMP) map.chg
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fit.chg:
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$(STAMP) fit.chg
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sta.chg:
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$(STAMP) sta.chg
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asm.chg:
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$(STAMP) asm.chg
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