Alex Forencich f6262c3606 fpga/mqnic: Update FIFO parameter naming ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2022-11-01 23:57:50 -07:00

..

app

fpga: Add clock info register block

2022-10-15 19:45:02 -07:00

common

fpga/mqnic: Update FIFO parameter naming

2022-11-01 23:57:50 -07:00

lib

merged changes in eth

2022-11-01 23:57:35 -07:00

mqnic

fpga/mqnic/fb2CG: Update placement constraints

2022-10-17 13:01:16 -07:00

build_images_project.ini

Rework build_images settings

2022-07-13 01:18:42 -07:00

build_images.py

fpga/build_images.py: update quartus message parsing

2022-08-04 13:40:34 -07:00

collect_utilization.py

Add build automation scripts

2022-03-02 23:20:59 -08:00

watch.sh

Change interval

2022-07-13 01:18:55 -07:00