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539 lines
16 KiB
Verilog
539 lines
16 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 10G Ethernet MAC/PHY combination with TX and RX FIFOs
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*/
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module eth_mac_phy_10g_fifo #
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(
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parameter DATA_WIDTH = 64,
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parameter HDR_WIDTH = (DATA_WIDTH/32),
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parameter AXIS_DATA_WIDTH = DATA_WIDTH,
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parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
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parameter ENABLE_PADDING = 1,
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parameter ENABLE_DIC = 1,
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parameter MIN_FRAME_LENGTH = 64,
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parameter BIT_REVERSE = 0,
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parameter SCRAMBLER_DISABLE = 0,
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parameter PRBS31_ENABLE = 0,
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parameter TX_SERDES_PIPELINE = 0,
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parameter RX_SERDES_PIPELINE = 0,
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parameter BITSLIP_HIGH_CYCLES = 1,
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parameter BITSLIP_LOW_CYCLES = 8,
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parameter COUNT_125US = 125000/6.4,
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parameter TX_FIFO_DEPTH = 4096,
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parameter TX_FIFO_RAM_PIPELINE = 1,
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parameter TX_FRAME_FIFO = 1,
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parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
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parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
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parameter TX_DROP_WHEN_FULL = 0,
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parameter RX_FIFO_DEPTH = 4096,
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parameter RX_FIFO_RAM_PIPELINE = 1,
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parameter RX_FRAME_FIFO = 1,
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parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
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parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
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parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME,
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parameter PTP_PERIOD_NS = 4'h6,
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parameter PTP_PERIOD_FNS = 16'h6666,
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parameter PTP_USE_SAMPLE_CLOCK = 0,
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parameter TX_PTP_TS_ENABLE = 0,
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parameter RX_PTP_TS_ENABLE = 0,
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parameter TX_PTP_TS_FIFO_DEPTH = 64,
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parameter PTP_TS_WIDTH = 96,
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parameter TX_PTP_TAG_ENABLE = 0,
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parameter PTP_TAG_WIDTH = 16,
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parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
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parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
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)
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(
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input wire rx_clk,
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input wire rx_rst,
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input wire tx_clk,
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input wire tx_rst,
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input wire logic_clk,
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input wire logic_rst,
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input wire ptp_sample_clk,
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/*
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* AXI input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
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input wire tx_axis_tvalid,
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output wire tx_axis_tready,
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input wire tx_axis_tlast,
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input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
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/*
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* Transmit timestamp output
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*/
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output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
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output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
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output wire m_axis_tx_ptp_ts_valid,
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input wire m_axis_tx_ptp_ts_ready,
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/*
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* AXI output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
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output wire rx_axis_tvalid,
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input wire rx_axis_tready,
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output wire rx_axis_tlast,
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output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
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/*
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* SERDES interface
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*/
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output wire [DATA_WIDTH-1:0] serdes_tx_data,
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output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
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input wire [DATA_WIDTH-1:0] serdes_rx_data,
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input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
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output wire serdes_rx_bitslip,
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output wire serdes_rx_reset_req,
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/*
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* Status
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*/
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output wire tx_error_underflow,
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output wire tx_fifo_overflow,
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output wire tx_fifo_bad_frame,
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output wire tx_fifo_good_frame,
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output wire rx_error_bad_frame,
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output wire rx_error_bad_fcs,
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output wire rx_bad_block,
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output wire rx_block_lock,
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output wire rx_high_ber,
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output wire rx_status,
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output wire rx_fifo_overflow,
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output wire rx_fifo_bad_frame,
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output wire rx_fifo_good_frame,
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/*
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* PTP clock
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*/
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input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
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input wire ptp_ts_step,
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/*
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* Configuration
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*/
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input wire [7:0] ifg_delay,
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input wire tx_prbs31_enable,
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input wire rx_prbs31_enable
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);
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parameter KEEP_WIDTH = DATA_WIDTH/8;
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wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
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wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
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wire tx_fifo_axis_tvalid;
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wire tx_fifo_axis_tready;
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wire tx_fifo_axis_tlast;
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wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
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wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
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wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
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wire rx_fifo_axis_tvalid;
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wire rx_fifo_axis_tlast;
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wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
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wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
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wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
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wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
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wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
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wire tx_axis_ptp_ts_valid;
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// synchronize MAC status signals into logic clock domain
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wire tx_error_underflow_int;
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reg [0:0] tx_sync_reg_1 = 1'b0;
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reg [0:0] tx_sync_reg_2 = 1'b0;
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reg [0:0] tx_sync_reg_3 = 1'b0;
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reg [0:0] tx_sync_reg_4 = 1'b0;
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assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
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always @(posedge tx_clk or posedge tx_rst) begin
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if (tx_rst) begin
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tx_sync_reg_1 <= 1'b0;
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end else begin
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tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
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end
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end
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always @(posedge logic_clk or posedge logic_rst) begin
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if (logic_rst) begin
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tx_sync_reg_2 <= 1'b0;
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tx_sync_reg_3 <= 1'b0;
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tx_sync_reg_4 <= 1'b0;
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end else begin
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tx_sync_reg_2 <= tx_sync_reg_1;
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tx_sync_reg_3 <= tx_sync_reg_2;
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tx_sync_reg_4 <= tx_sync_reg_3;
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end
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end
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wire rx_error_bad_frame_int;
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wire rx_error_bad_fcs_int;
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wire rx_bad_block_int;
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wire rx_block_lock_int;
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wire rx_high_ber_int;
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wire rx_status_int;
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reg [5:0] rx_sync_reg_1 = 6'd0;
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reg [5:0] rx_sync_reg_2 = 6'd0;
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reg [5:0] rx_sync_reg_3 = 6'd0;
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reg [5:0] rx_sync_reg_4 = 6'd0;
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assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
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assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
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assign rx_bad_block = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
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assign rx_block_lock = rx_sync_reg_4[3];
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assign rx_high_ber = rx_sync_reg_4[4];
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assign rx_status = rx_sync_reg_4[5];
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always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= 6'd0;
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end else begin
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rx_sync_reg_1[0] <= rx_sync_reg_1[0] ^ rx_error_bad_frame_int;
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rx_sync_reg_1[1] <= rx_sync_reg_1[1] ^ rx_error_bad_fcs_int;
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rx_sync_reg_1[2] <= rx_sync_reg_1[2] ^ rx_bad_block_int;
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rx_sync_reg_1[3] <= rx_block_lock_int;
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rx_sync_reg_1[4] <= rx_high_ber_int;
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rx_sync_reg_1[5] <= rx_status_int;
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end
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end
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always @(posedge logic_clk or posedge logic_rst) begin
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if (logic_rst) begin
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rx_sync_reg_2 <= 6'd0;
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rx_sync_reg_3 <= 6'd0;
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rx_sync_reg_4 <= 6'd0;
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end else begin
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rx_sync_reg_2 <= rx_sync_reg_1;
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rx_sync_reg_3 <= rx_sync_reg_2;
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rx_sync_reg_4 <= rx_sync_reg_3;
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end
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end
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// PTP timestamping
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generate
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if (TX_PTP_TS_ENABLE) begin : tx_ptp
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ptp_clock_cdc #(
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.TS_WIDTH(PTP_TS_WIDTH),
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.NS_WIDTH(6),
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.FNS_WIDTH(16),
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.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
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)
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tx_ptp_cdc (
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.input_clk(logic_clk),
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.input_rst(logic_rst),
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.output_clk(tx_clk),
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.output_rst(tx_rst),
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.sample_clk(ptp_sample_clk),
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.input_ts(ptp_ts_96),
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.input_ts_step(ptp_ts_step),
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.output_ts(tx_ptp_ts_96),
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.output_ts_step(),
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.output_pps(),
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.locked()
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);
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axis_async_fifo #(
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.DEPTH(TX_PTP_TS_FIFO_DEPTH),
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.DATA_WIDTH(PTP_TS_WIDTH),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(0),
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.ID_ENABLE(TX_PTP_TAG_ENABLE),
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.ID_WIDTH(PTP_TAG_WIDTH),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.FRAME_FIFO(0)
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)
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tx_ptp_ts_fifo (
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// AXI input
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.s_clk(tx_clk),
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.s_rst(tx_rst),
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.s_axis_tdata(tx_axis_ptp_ts_96),
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.s_axis_tkeep(0),
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.s_axis_tvalid(tx_axis_ptp_ts_valid),
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.s_axis_tready(),
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.s_axis_tlast(0),
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.s_axis_tid(tx_axis_ptp_ts_tag),
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.s_axis_tdest(0),
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.s_axis_tuser(0),
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// AXI output
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.m_clk(logic_clk),
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.m_rst(logic_rst),
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.m_axis_tdata(m_axis_tx_ptp_ts_96),
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.m_axis_tkeep(),
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.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
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.m_axis_tready(m_axis_tx_ptp_ts_ready),
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.m_axis_tlast(),
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.m_axis_tid(m_axis_tx_ptp_ts_tag),
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.m_axis_tdest(),
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.m_axis_tuser(),
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// Status
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.s_status_overflow(),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_overflow(),
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.m_status_bad_frame(),
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.m_status_good_frame()
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);
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end else begin
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assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
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assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
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assign m_axis_tx_ptp_ts_valid = 1'b0;
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assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
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end
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if (RX_PTP_TS_ENABLE) begin : rx_ptp
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ptp_clock_cdc #(
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.TS_WIDTH(PTP_TS_WIDTH),
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.NS_WIDTH(6),
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.FNS_WIDTH(16),
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.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
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)
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rx_ptp_cdc (
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.input_clk(logic_clk),
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.input_rst(logic_rst),
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.output_clk(rx_clk),
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.output_rst(rx_rst),
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.sample_clk(ptp_sample_clk),
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.input_ts(ptp_ts_96),
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.input_ts_step(ptp_ts_step),
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.output_ts(rx_ptp_ts_96),
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.output_ts_step(),
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.output_pps(),
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.locked()
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);
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end else begin
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assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
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end
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endgenerate
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eth_mac_phy_10g #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_WIDTH(KEEP_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.ENABLE_PADDING(ENABLE_PADDING),
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.ENABLE_DIC(ENABLE_DIC),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
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.PTP_PERIOD_NS(PTP_PERIOD_NS),
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.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
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.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
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.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
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.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
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.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
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.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
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.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
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.TX_USER_WIDTH(TX_USER_WIDTH),
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.RX_USER_WIDTH(RX_USER_WIDTH),
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.BIT_REVERSE(BIT_REVERSE),
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.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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eth_mac_phy_10g_inst (
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.tx_clk(tx_clk),
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.tx_rst(tx_rst),
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.rx_clk(rx_clk),
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.rx_rst(rx_rst),
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.tx_axis_tdata(tx_fifo_axis_tdata),
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.tx_axis_tkeep(tx_fifo_axis_tkeep),
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.tx_axis_tvalid(tx_fifo_axis_tvalid),
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.tx_axis_tready(tx_fifo_axis_tready),
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.tx_axis_tlast(tx_fifo_axis_tlast),
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.tx_axis_tuser(tx_fifo_axis_tuser),
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.rx_axis_tdata(rx_fifo_axis_tdata),
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.rx_axis_tkeep(rx_fifo_axis_tkeep),
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.rx_axis_tvalid(rx_fifo_axis_tvalid),
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.rx_axis_tlast(rx_fifo_axis_tlast),
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.rx_axis_tuser(rx_fifo_axis_tuser),
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.serdes_tx_data(serdes_tx_data),
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.serdes_tx_hdr(serdes_tx_hdr),
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.serdes_rx_data(serdes_rx_data),
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.serdes_rx_hdr(serdes_rx_hdr),
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.serdes_rx_bitslip(serdes_rx_bitslip),
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.serdes_rx_reset_req(serdes_rx_reset_req),
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.tx_ptp_ts(tx_ptp_ts_96),
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.rx_ptp_ts(rx_ptp_ts_96),
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.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
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.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
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.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
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.tx_error_underflow(tx_error_underflow_int),
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.rx_error_bad_frame(rx_error_bad_frame_int),
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.rx_error_bad_fcs(rx_error_bad_fcs_int),
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.rx_bad_block(rx_bad_block_int),
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.rx_block_lock(rx_block_lock_int),
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.rx_high_ber(rx_high_ber_int),
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.rx_status(rx_status_int),
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.ifg_delay(ifg_delay),
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.tx_prbs31_enable(tx_prbs31_enable),
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.rx_prbs31_enable(rx_prbs31_enable)
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);
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axis_async_fifo_adapter #(
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.DEPTH(TX_FIFO_DEPTH),
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.S_DATA_WIDTH(AXIS_DATA_WIDTH),
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.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
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.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.M_DATA_WIDTH(DATA_WIDTH),
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.M_KEEP_ENABLE(1),
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.M_KEEP_WIDTH(KEEP_WIDTH),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(1),
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|
.USER_WIDTH(TX_USER_WIDTH),
|
|
.RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
|
|
.FRAME_FIFO(TX_FRAME_FIFO),
|
|
.USER_BAD_FRAME_VALUE(1'b1),
|
|
.USER_BAD_FRAME_MASK(1'b1),
|
|
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
|
|
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
|
|
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
|
|
)
|
|
tx_fifo (
|
|
// AXI input
|
|
.s_clk(logic_clk),
|
|
.s_rst(logic_rst),
|
|
.s_axis_tdata(tx_axis_tdata),
|
|
.s_axis_tkeep(tx_axis_tkeep),
|
|
.s_axis_tvalid(tx_axis_tvalid),
|
|
.s_axis_tready(tx_axis_tready),
|
|
.s_axis_tlast(tx_axis_tlast),
|
|
.s_axis_tid(0),
|
|
.s_axis_tdest(0),
|
|
.s_axis_tuser(tx_axis_tuser),
|
|
// AXI output
|
|
.m_clk(tx_clk),
|
|
.m_rst(tx_rst),
|
|
.m_axis_tdata(tx_fifo_axis_tdata),
|
|
.m_axis_tkeep(tx_fifo_axis_tkeep),
|
|
.m_axis_tvalid(tx_fifo_axis_tvalid),
|
|
.m_axis_tready(tx_fifo_axis_tready),
|
|
.m_axis_tlast(tx_fifo_axis_tlast),
|
|
.m_axis_tid(),
|
|
.m_axis_tdest(),
|
|
.m_axis_tuser(tx_fifo_axis_tuser),
|
|
// Status
|
|
.s_status_overflow(tx_fifo_overflow),
|
|
.s_status_bad_frame(tx_fifo_bad_frame),
|
|
.s_status_good_frame(tx_fifo_good_frame),
|
|
.m_status_overflow(),
|
|
.m_status_bad_frame(),
|
|
.m_status_good_frame()
|
|
);
|
|
|
|
axis_async_fifo_adapter #(
|
|
.DEPTH(RX_FIFO_DEPTH),
|
|
.S_DATA_WIDTH(DATA_WIDTH),
|
|
.S_KEEP_ENABLE(1),
|
|
.S_KEEP_WIDTH(KEEP_WIDTH),
|
|
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
|
|
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.ID_ENABLE(0),
|
|
.DEST_ENABLE(0),
|
|
.USER_ENABLE(1),
|
|
.USER_WIDTH(RX_USER_WIDTH),
|
|
.RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
|
|
.FRAME_FIFO(RX_FRAME_FIFO),
|
|
.USER_BAD_FRAME_VALUE(1'b1),
|
|
.USER_BAD_FRAME_MASK(1'b1),
|
|
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
|
|
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
|
|
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
|
|
)
|
|
rx_fifo (
|
|
// AXI input
|
|
.s_clk(rx_clk),
|
|
.s_rst(rx_rst),
|
|
.s_axis_tdata(rx_fifo_axis_tdata),
|
|
.s_axis_tkeep(rx_fifo_axis_tkeep),
|
|
.s_axis_tvalid(rx_fifo_axis_tvalid),
|
|
.s_axis_tready(),
|
|
.s_axis_tlast(rx_fifo_axis_tlast),
|
|
.s_axis_tid(0),
|
|
.s_axis_tdest(0),
|
|
.s_axis_tuser(rx_fifo_axis_tuser),
|
|
// AXI output
|
|
.m_clk(logic_clk),
|
|
.m_rst(logic_rst),
|
|
.m_axis_tdata(rx_axis_tdata),
|
|
.m_axis_tkeep(rx_axis_tkeep),
|
|
.m_axis_tvalid(rx_axis_tvalid),
|
|
.m_axis_tready(rx_axis_tready),
|
|
.m_axis_tlast(rx_axis_tlast),
|
|
.m_axis_tid(),
|
|
.m_axis_tdest(),
|
|
.m_axis_tuser(rx_axis_tuser),
|
|
// Status
|
|
.s_status_overflow(),
|
|
.s_status_bad_frame(),
|
|
.s_status_good_frame(),
|
|
.m_status_overflow(rx_fifo_overflow),
|
|
.m_status_bad_frame(rx_fifo_bad_frame),
|
|
.m_status_good_frame(rx_fifo_good_frame)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|