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corundum/fpga/common/rtl
History
Alex Forencich f7a1a7ef95 Add descriptor FIFOs
2020-03-07 22:28:59 -08:00
..
cmac_pad.v
Update cmac_pad to pad frames to 60 bytes
2020-02-26 13:36:19 -08:00
cpl_op_mux.v
Add completion op mux module
2019-09-23 14:47:09 -07:00
cpl_queue_manager.v
Update pipelining to enable URAM inference
2019-12-28 01:13:57 -08:00
cpl_write.v
Use new DMA subsystem
2019-10-17 16:02:14 -07:00
desc_fetch.v
Use new DMA subsystem
2019-10-17 16:02:14 -07:00
desc_op_mux.v
Add descriptor op mux module
2019-09-23 14:47:00 -07:00
event_mux.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
interface.v
Fix signal sizing bug
2020-03-06 00:24:13 -08:00
port.v
Add descriptor FIFOs
2020-03-07 22:28:59 -08:00
queue_manager.v
Update pipelining to enable URAM inference
2019-12-28 01:13:57 -08:00
rx_checksum.v
Parametrize checksum offload
2019-11-13 23:49:50 -08:00
rx_engine.v
Add RSS support
2019-12-06 14:15:16 -08:00
rx_hash.v
Add rx_hash module and testbenches
2019-12-05 13:47:07 -08:00
tdma_ber_ch.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_ber.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_scheduler.v
Update TDMA scheduler to generate status signals and avoid producing runt outputs
2019-11-05 16:55:19 -08:00
tx_checksum.v
Parametrize checksum offload
2019-11-13 23:49:50 -08:00
tx_engine.v
Reserve packet data slot early and release on dequeue fail
2019-12-30 17:49:42 -08:00
tx_scheduler_ctrl_tdma.v
Add tx_scheduler_ctrl_tdma module
2019-11-05 18:24:22 -08:00
tx_scheduler_rr.v
Remove unused table fields
2019-12-30 22:02:22 -08:00