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123 lines
3.1 KiB
Verilog
123 lines
3.1 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for ptp_perout
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*/
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module test_ptp_perout;
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// Parameters
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parameter FNS_ENABLE = 1;
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parameter OUT_START_S = 48'h0;
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parameter OUT_START_NS = 30'h0;
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parameter OUT_START_FNS = 16'h0000;
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parameter OUT_PERIOD_S = 48'd1;
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parameter OUT_PERIOD_NS = 30'd0;
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parameter OUT_PERIOD_FNS = 16'h0000;
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parameter OUT_WIDTH_S = 48'h0;
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parameter OUT_WIDTH_NS = 30'd1000;
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parameter OUT_WIDTH_FNS = 16'h0000;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [95:0] input_ts_96 = 0;
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reg input_ts_step = 0;
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reg enable = 0;
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reg [95:0] input_start = 0;
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reg input_start_valid = 0;
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reg [95:0] input_period = 0;
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reg input_period_valid = 0;
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reg [95:0] input_width = 0;
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reg input_width_valid = 0;
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// Outputs
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wire locked;
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wire error;
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wire output_pulse;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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input_ts_96,
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input_ts_step,
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enable,
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input_start,
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input_start_valid,
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input_period,
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input_period_valid,
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input_width,
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input_width_valid
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);
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$to_myhdl(
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locked,
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error,
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output_pulse
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);
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// dump file
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$dumpfile("test_ptp_perout.lxt");
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$dumpvars(0, test_ptp_perout);
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end
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ptp_perout #(
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.FNS_ENABLE(FNS_ENABLE),
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.OUT_START_S(OUT_START_S),
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.OUT_START_NS(OUT_START_NS),
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.OUT_START_FNS(OUT_START_FNS),
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.OUT_PERIOD_S(OUT_PERIOD_S),
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.OUT_PERIOD_NS(OUT_PERIOD_NS),
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.OUT_PERIOD_FNS(OUT_PERIOD_FNS),
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.OUT_WIDTH_S(OUT_WIDTH_S),
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.OUT_WIDTH_NS(OUT_WIDTH_NS),
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.OUT_WIDTH_FNS(OUT_WIDTH_FNS)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.input_ts_96(input_ts_96),
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.input_ts_step(input_ts_step),
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.enable(enable),
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.input_start(input_start),
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.input_start_valid(input_start_valid),
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.input_period(input_period),
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.input_period_valid(input_period_valid),
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.input_width(input_width),
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.input_width_valid(input_width_valid),
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.locked(locked),
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.error(error),
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.output_pulse(output_pulse)
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);
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endmodule
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