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Perfect version about cmos design with fpga

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jiaowushuang 2017-11-11 11:15:49 +08:00
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity DPA is
port(Clk_DDR: std_logic;
Clk_DDR_Div: std_logic;
Cmd_Training:in std_logic; ----training command
LVDS_IN_P:in std_logic; ----LVDS data
LVDS_IN_N:in std_logic;
Training_Done:out std_logic; ----Training finish
LVDS_Dout:out std_logic_vector (11 downto 0); ----LVDS Dout
LVDS_Clk:out std_logic;
LVDS_Dlen_n:out std_logic ----LVDS Clk
);
end DPA;
architecture Behavioral of DPA is
signal Clk_DDR_Rst_n:std_logic:='0';
signal Cnt_DDR_Rst_n:integer range 0 to 255:=0;
signal Iserdes_Dlyce:std_logic:='0';
signal Iserdes_Dlyrst:std_logic:='0';
signal Iserdes_Bitslip:std_logic:='0';
signal Tem_LVDS_OUT:std_logic_vector(11 downto 0);
signal Cmd_Training_r,Cmd_Training_rr,Cmd_Training_rrr,Cmd_Training_rrrr:std_logic:='0';
signal Tri_Cmd_Training:std_logic:='0';
type FSM_Align is (S_IDLE, S_RESET_1, S_RESET_2, S_WORD_ALIGN, S_FINISH,
S_EYE_SAMPLE, S_EYE_CHECK, S_EYE_DELAY, S_EYE_CALC, S_EYE_CENTER);
type FSM_Eye is (S_FIND_EDGE_1, S_EDGE_1, S_FIND_EDGE_2);
signal Eye_State: FSM_Eye := S_FIND_EDGE_1;
signal Align_Ctl_State: FSM_Align := S_IDLE;
signal Cnt_Align:integer range 0 to 15:=0;
signal Data_Stable:std_logic := '0';
signal Cnt_Step:integer range 0 to 127:=0;
signal Cnt_Error:integer range 0 to 7:=0;
signal Cnt_Sample:integer range 0 to 15:=0;
signal Data_Curr:std_logic_vector (11 downto 0) := (others => '0');
signal Data_Prev:std_logic_vector (11 downto 0) := (others => '0');
signal Loc_Eye_Start:integer range 0 to 127:=0;
signal Loc_Eye_Mid:integer range 0 to 127:=0;
signal Loc_Eye_End:integer range 0 to 127:=0;
signal Cnt_Bitslip:integer range 0 to 15;
constant Training_Word : std_logic_vector(11 downto 0) := x"719";
component IDB is
port (Data_Ser_p:in std_logic;
Data_Ser_N:in std_logic;
Clk_DDR_Div:in std_logic;
Clk_DDR:in std_logic;
Dlyce:in std_logic;
Dlyrst:in std_logic;
Bitslip:in std_logic;
Data_Par:out std_logic_vector(11 downto 0);
Data_Len_n:out std_logic
);
end component;
begin
LVDS_Clk<=Clk_DDR;
------------------------------
process(Clk_DDR_Div) begin
if rising_edge(Clk_DDR_Div) then
if Cnt_DDR_Rst_n=255 then
Cnt_DDR_Rst_n<=255;
else
Cnt_DDR_Rst_n<=Cnt_DDR_Rst_n+1;
end if;
case Cnt_DDR_Rst_n is
when 255 =>
Clk_DDR_Rst_n<='1';
when others =>
Clk_DDR_Rst_n<='0';
end case;
end if;
end process;
Inst_IDB: IDB
port map(Data_Ser_p=>LVDS_IN_P,
Data_Ser_N=>LVDS_IN_N,
Clk_DDR_Div=>Clk_DDR_Div,
Clk_DDR=>Clk_DDR,
Dlyce=>Iserdes_Dlyce,
Dlyrst=>Iserdes_Dlyrst,
Bitslip=>Iserdes_Bitslip,
Data_Par=>Tem_LVDS_OUT,
Data_Len_n=>LVDS_Dlen_n
);
Data_Curr<=Tem_LVDS_OUT;
LVDS_Dout<=Tem_LVDS_OUT;
process(Clk_DDR_Div) begin
if rising_edge(Clk_DDR_Div) then
Cmd_Training_r<=Cmd_Training;
Cmd_Training_rr<=Cmd_Training_r;
Cmd_Training_rrr<=Cmd_Training_rr;
Cmd_Training_rrrr<=Cmd_Training_rrr;
end if;
end process;
process(Clk_DDR_Div) begin
if rising_edge(Clk_DDR_Div) then
if Cmd_Training_rrrr='0' and Cmd_Training_rrr='1' then
Tri_Cmd_Training<='1';
else
Tri_Cmd_Training<='0';
end if;
end if;
end process;
--------------------------------------------------------------dynamic ajust
process (Clk_DDR_Div) begin
if (Clk_DDR_Div'event and Clk_DDR_Div = '1') then
if (Clk_DDR_Rst_n = '0') then
Align_Ctl_State<=S_IDLE;
Eye_State<=S_FIND_EDGE_1;
Cnt_Align<= 0;
Cnt_Step<= 0;
Cnt_Error<= 0;
Cnt_Sample<= 0;
Data_Prev<= (others => '0');
Data_Stable<= '1';
Iserdes_Dlyce<= '0';
Iserdes_Dlyrst<= '0';
Iserdes_Bitslip<= '0';
Loc_Eye_Start<=0;
Loc_Eye_Mid<=0;
Loc_Eye_End<=0;
Cnt_Bitslip<=0;
Training_Done<='0';
else
Iserdes_Dlyrst <= '0';
Iserdes_Dlyce <= '0';
Iserdes_Bitslip <= '0';
case Align_Ctl_State is
when S_IDLE =>
if Tri_Cmd_Training = '1' then
Align_Ctl_State <= S_RESET_1;
Training_Done<='1';
end if;
Cnt_Bitslip<=0;
Cnt_Align<= 15;
Cnt_Step<= 0;
Loc_Eye_Start <= 0;
Loc_Eye_Mid<=0;
Loc_Eye_End<=0;
when S_RESET_1 => ----first reset
if (Cnt_Align = 0) then
Align_Ctl_State <= S_EYE_SAMPLE;
Eye_State <= S_FIND_EDGE_1;
Data_Stable <= '1';
Data_Prev <= Data_Curr;
Cnt_Sample <= 15;
Cnt_Error <= 0;
else
Cnt_Align <= Cnt_Align - 1;
end if;
if (Cnt_Align = 15) then ----the first cycle reset iserdes
Iserdes_Dlyrst <= '1';
end if;
when S_EYE_SAMPLE => ----to find the transition
if (Cnt_Sample = 0) then
Data_Prev <= Data_Curr; ----compare 16 times,if not vary,then move one delay
Align_Ctl_State <= S_EYE_DELAY;
Cnt_Align <= 15; -----if there is a vary,then catch the edge
else
Cnt_Sample <= Cnt_Sample - 1;
end if;
if (Data_Curr /= Data_Prev) then -----data transition
Data_Stable <= '0';
end if;
when S_EYE_DELAY =>
if (Cnt_Align = 15) then
Iserdes_Dlyce <= '1';
end if;
if (Cnt_Align = 0) then
Align_Ctl_State <= S_EYE_CHECK;
else
Cnt_Align <= Cnt_Align - 1;
end if;
--
when S_EYE_CHECK => ----if find the edge,then catch the steps,if not,move on ,to eye sample
case Cnt_Step is
when 63 =>
Align_Ctl_State <= S_EYE_CALC;
case Eye_State is
when S_FIND_EDGE_1 =>
Loc_Eye_Start <= 0;
Loc_Eye_End <= 63;
when S_EDGE_1 =>
Loc_Eye_Start <= 0;
Loc_Eye_End <= 0;
when S_FIND_EDGE_2 =>
case Loc_Eye_Start is
when 0 to 28 =>
Loc_Eye_Start <= 63;
Loc_Eye_End <= 63;
when others =>
Loc_Eye_Start <= 0;
Loc_Eye_End <= 0;
end case;
when others =>
Cnt_Step<=0;
end case;
when others =>
case Cnt_Error is ---Cnt_Error:if catch the edge,make the data delay 8 cycle to find the next edge
when 0 =>
case Eye_State is
when S_FIND_EDGE_1 =>
if (Data_Stable = '0') then
Eye_State <= S_EDGE_1;
Cnt_Error <= 7;
Loc_Eye_Start <= Cnt_Step;
end if;
Align_Ctl_State<= S_EYE_SAMPLE;
when S_EDGE_1 =>
if Data_Stable = '1' then
Eye_State <= S_FIND_EDGE_2;
Cnt_Error <= 0;
end if;
Align_Ctl_State<= S_EYE_SAMPLE;
when S_FIND_EDGE_2 =>
if Data_Stable = '0' then
Align_Ctl_State <= S_EYE_CALC;
Loc_Eye_End <= Cnt_Step;
else
Align_Ctl_State<= S_EYE_SAMPLE;
end if;
when others =>
Eye_State<=S_FIND_EDGE_1;
end case;
when others =>
Align_Ctl_State<= S_EYE_SAMPLE;
Data_Stable <= '1';
end case;
Cnt_Step <= Cnt_Step + 1;
end case;
Cnt_Sample <= 15;
Data_Stable <= '1';
if (Cnt_Error /= 0) then
Cnt_Error<= Cnt_Error - 1;
end if;
when S_EYE_CALC =>
Align_Ctl_State <= S_RESET_2;
Cnt_Align <= 15;
-- Sum <= Loc_Eye_Start + Loc_Eye_End;
Loc_Eye_Mid <= conv_integer("00" & conv_std_logic_vector(Loc_Eye_Start+Loc_Eye_End,7)(6 downto 1));-----(start + end )/2
Cnt_Step<= conv_integer("00" & conv_std_logic_vector(Loc_Eye_Start+Loc_Eye_End,7)(6 downto 1));
when S_RESET_2 =>
if (Cnt_Align=15) then
Iserdes_Dlyrst<='1';
end if;
if Cnt_Align=0 then
Align_Ctl_State<= S_EYE_CENTER;
Cnt_Align<= 15;
else
Cnt_Align<= Cnt_Align - 1;
end if;
------
when S_EYE_CENTER => ----turn back to data center
if Cnt_Align = 15 then
Iserdes_Dlyce<= '1';
end if;
if Cnt_Align = 0 then
case Cnt_Step is
when 0 | 1 =>
Align_Ctl_State<=S_WORD_ALIGN;
Cnt_Align<= 0;
Cnt_Step<= 0;
when others =>
Cnt_Step<= Cnt_Step - 1;
Cnt_Align<= 15;
end case;
else
Cnt_Align<=Cnt_Align - 1;
end if;
when S_WORD_ALIGN =>
if Cnt_Align = 0 then
if Data_Curr = Training_Word then
Align_Ctl_State<= S_FINISH;
else
if Cnt_Bitslip=15 then
Align_Ctl_State<=S_IDLE;
else
Iserdes_Bitslip<= '1';
Cnt_Align<=15;
Cnt_Bitslip<=Cnt_Bitslip+1;
end if;
end if;
else
Cnt_Align<=Cnt_Align-1;
end if;
when S_FINISH =>
Training_Done<='1';
Align_Ctl_State <= S_IDLE;
end case;
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
-- <20><>ģ<EFBFBD><C4A3><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>Bitslip<69>Ĺ<EFBFBD><C4B9>̣<EFBFBD><CCA3>ٶ<EFBFBD>Ӧ<EFBFBD>úܿ<C3BA>
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity IDB is
port (Data_Ser_p:in std_logic;
Data_Ser_N:in std_logic;
Clk_DDR_Div:in std_logic;
Clk_DDR:in std_logic;
Dlyce:in std_logic;
Dlyrst:in std_logic;
Bitslip:in std_logic;
Data_Par:out std_logic_vector(11 downto 0);
Data_Len_n:out std_logic
);
end IDB;
architecture Behavioral of IDB is
signal Cnt_DDR_Rst:integer range 0 to 255:=0;
signal Rst_DDR_n:std_logic:='0';
signal Data_Ser : std_logic;
signal Data_Ser_Dly : std_logic; ----serial data with delay time
signal Bitslip_r,Bitslip_rr,Bitslip_rrr,Bitslip_rrrr : std_logic := '0';
signal Bitslip_req : std_logic := '0';
signal Bitslip_even : std_logic := '0';
signal Iddr_Q1 : std_logic;
signal Iddr_Q2 : std_logic;
signal Data_1 : std_logic;
signal Data_2 : std_logic;
signal Data_2_q : std_logic;
signal Load_Parallel : std_logic := '0';
signal Shift_Timer : std_logic_vector ( 4 downto 0):= (others => '1');
signal Shift_Data : std_logic_vector (11 downto 0):= (others => '0');
signal ClkPipeline : std_logic_vector(2 downto 0):=(others =>'1');
signal Data_Par_Temp : std_logic_vector (11 downto 0):= (others => '0');
signal Tem_Data_Len_n:std_logic:='1';
begin
Data_Len_n<=Tem_Data_Len_n;
inst_ibufds: IBUFDS
generic map (IOSTANDARD => "LVDS_25",
DIFF_TERM => true)
port map(i=> Data_Ser_p,
ib=> Data_Ser_N,
o=> Data_Ser
);
-- 64-tap<61>ӳ<EFBFBD><D3B3><EFBFBD> <20><>̬<EFBFBD><CCAC><EFBFBD><EFBFBD>
inst_idelay: IDELAY
generic map (IOBDELAY_TYPE=> "VARIABLE",
IOBDELAY_VALUE=> 0)
port map(i=> Data_Ser,
o => Data_Ser_Dly,
inc=> '1',
rst=> Dlyrst,
ce=> Dlyce,
c=> Clk_DDR_Div
);
-- DDR ˫<><CBAB>ʱ<EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD>
inst_iddr: IDDR
generic map (DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
INIT_Q1=> '0',
INIT_Q2=> '0',
SRTYPE=> "SYNC"
)
port map (d=> Data_Ser_Dly,
q1=> Iddr_Q1,
q2=> Iddr_Q2,
c=> Clk_DDR,
r=> '0',
s => '0',
ce=> '1'
);
process(Clk_DDR) begin
if rising_edge(Clk_DDR) then
if Cnt_DDR_Rst=255 then
Cnt_DDR_Rst<=255;
else
Cnt_DDR_Rst<=Cnt_DDR_Rst+1;
end if;
case Cnt_DDR_Rst is
when 255 =>
Rst_DDR_n<='1';
when others =>
Rst_DDR_n<='0';
end case;
end if;
end process;
process(Clk_DDR) begin
if rising_edge(Clk_DDR) then
Bitslip_r<=Bitslip;
Bitslip_rr<=Bitslip_r;
Bitslip_rrr<=Bitslip_rr;
Bitslip_rrrr<=Bitslip_rrr;
end if;
end process;
process (Clk_DDR) begin
if rising_edge(Clk_DDR) then
if (Rst_DDR_n = '0') then
Bitslip_req <= '0';
Bitslip_even <= '0';
Load_Parallel <= '0';
Data_1 <= '0';
Data_2 <= '0';
Data_2_q <= '0';
Shift_Timer <= (others => '1');
Shift_Data <= (others => '0');
Data_Par <= (others => '0');
Tem_Data_Len_n<='1';
else
if (Bitslip_rrr = '1' and Bitslip_rrrr = '0') then -----catch rising edge of Bitslip
if (Bitslip_even = '0') then
Bitslip_even <= '1';
Bitslip_req <= '1';
else
Bitslip_even <= '0';
end if;
end if;
Shift_Timer <= '0' & Shift_Timer(Shift_Timer'high downto 1);
if (Shift_Timer (2 downto 0) = "000") then ---every 6 times
Shift_Timer <= (others => '1');
Load_Parallel <= '1';
elsif (Shift_Timer (2 downto 0) = "001") then ----every 5 times
if (Bitslip_req = '1') then
Shift_Timer <= (others => '1');
Bitslip_req <= '0';
Load_Parallel <= '0';
end if;
else
Load_Parallel <= '0';
end if;
-- Safety measure to prevent lock-up situations
if (Shift_Timer (2 downto 0) = "000") then
Shift_Timer <= (others => '1');
Load_Parallel <= '1';
end if;
Data_1 <= Iddr_Q1;
Data_2 <= Iddr_Q2;
Data_2_q <= Data_2;
if (Bitslip_even = '1') then
Shift_Data <= Data_2 & Data_1 & Shift_Data(Shift_Data'high downto 2);
else
Shift_Data <= Data_1 & Data_2_q & Shift_Data(Shift_Data'high downto 2);
end if;
-- COPY SHIFT REGISTER TO PARALLEL DATA OUTPUT
if (Load_Parallel = '1') then
Data_Par_Temp <= Shift_Data;
end if;
-- Phase adjust towards rising edge of parallel clock
if ClkPipeline(1) = '1' and ClkPipeline(2) = '0' then
Data_Par(11) <= Data_Par_Temp(0);
Data_Par(10) <= Data_Par_Temp(1);
Data_Par(9) <= Data_Par_Temp(2);
Data_Par(8) <= Data_Par_Temp(3);
Data_Par(7) <= Data_Par_Temp(4);
Data_Par(6) <= Data_Par_Temp(5);
Data_Par(5) <= Data_Par_Temp(6);
Data_Par(4) <= Data_Par_Temp(7);
Data_Par(3) <= Data_Par_Temp(8);
Data_Par(2) <= Data_Par_Temp(9);
Data_Par(1) <= Data_Par_Temp(10);
Data_Par(0) <= Data_Par_Temp(11);
-- Data_Par<=Data_Par_Temp;
Tem_Data_Len_n<='0';
else
Tem_Data_Len_n<='1';
end if;
ClkPipeline <= ClkPipeline(1 downto 0) & Clk_DDR_Div;
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:47:44 03/06/2017
-- Design Name:
-- Module Name: IND_M - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity IND_M is
port(Clk200m:in std_logic; -----for IDELAYCTRL
CLK200M_Rst:in std_logic;
LVDS_IN_CLK_P:in std_logic; ----LVDS CLK
LVDS_IN_CLK_N:in std_logic;
Cmd_Training:in std_logic;
LVDS_IN_P:in std_logic_vector(11 downto 0);
LVDS_IN_N:in std_logic_vector(11 downto 0);
LVDS_OUT1:out std_logic_vector(11 downto 0);
LVDS_OUT2:out std_logic_vector(11 downto 0);
LVDS_OUT3:out std_logic_vector(11 downto 0);
LVDS_OUT4:out std_logic_vector(11 downto 0);
LVDS_OUT5:out std_logic_vector(11 downto 0);
LVDS_OUT6:out std_logic_vector(11 downto 0);
LVDS_OUT7:out std_logic_vector(11 downto 0);
LVDS_OUT8:out std_logic_vector(11 downto 0);
LVDS_OUT9:out std_logic_vector(11 downto 0);
LVDS_OUT10:out std_logic_vector(11 downto 0);
LVDS_OUT11:out std_logic_vector(11 downto 0);
LVDS_OUT12:out std_logic_vector(11 downto 0);
LVDS_OUT_Clk:out std_logic;
Training_Done:out std_logic_vector(11 downto 0);
LVDS_OUT_Dlen_n:out std_logic_vector(11 downto 0)
);
end IND_M;
architecture Behavioral of IND_M is
signal Clk_DDR:std_logic:='0';
signal Tem_Clk_DDR:std_logic:='0';
signal Clk_DDR_DIV:std_logic:='0';
signal Tem_Clk_DDR_DIV:std_logic:='0';
signal Cnt_DDRDIV:integer range 0 to 5:=0;
signal Training_Down:std_logic;
signal LVDS_Datain_P:std_logic_vector(11 downto 0);
signal LVDS_Datain_N:std_logic_vector(11 downto 0);
signal LVDS_OUT_Dlen:std_logic:='1';
type Tem_Data is array(11 downto 0) of std_logic_vector(11 downto 0);
signal Tem_LVDS_OUT:Tem_Data:=(others=>(others=>'0'));
component DPA is
port(Clk_DDR: std_logic;
Clk_DDR_Div: std_logic;
Cmd_Training:in std_logic; ----training command
LVDS_IN_P:in std_logic; ----LVDS data
LVDS_IN_N:in std_logic;
Training_Done:out std_logic; ----Training finish
LVDS_Dout:out std_logic_vector (11 downto 0); ----LVDS Out
LVDS_Clk:out std_logic;
LVDS_Dlen_n:out std_logic ----LVDS Clk
);
end component;
-- attribute loc:string;
-- attribute loc of u1:label is "IDELAYCTRL_X0Y3";
begin
LVDS_OUT_Clk<=Clk_DDR;
LVDS_OUT1<=Tem_LVDS_OUT(0);
LVDS_OUT2<=Tem_LVDS_OUT(1);
LVDS_OUT3<=Tem_LVDS_OUT(2);
LVDS_OUT4<=Tem_LVDS_OUT(3);
LVDS_OUT5<=Tem_LVDS_OUT(4);
LVDS_OUT6<=Tem_LVDS_OUT(5);
LVDS_OUT7<=Tem_LVDS_OUT(6);
LVDS_OUT8<=Tem_LVDS_OUT(7);
LVDS_OUT9<=Tem_LVDS_OUT(8);
LVDS_OUT10<=Tem_LVDS_OUT(9);
LVDS_OUT11<=Tem_LVDS_OUT(10);
LVDS_OUT12<=Tem_LVDS_OUT(11);
-- u1: IDELAYCTRL
-- port map (rst => Clk200m_Rst,
-- refclk => Clk200m);
u2: IBUFGDS
generic map (IOSTANDARD=> "DEFAULT")
port map (i=> LVDS_IN_CLK_P,
ib=> LVDS_IN_CLK_N,
o=> Tem_Clk_DDR
);
u3 : BUFR
generic map (
BUFR_DIVIDE => "1", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
SIM_DEVICE => "VIRTEX5") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6"
port map (
O =>Clk_DDR , -- Clock buffer output
CE => '1', -- Clock enable input
CLR => '0', -- Clock buffer reset input
I => Tem_Clk_DDR -- Clock buffer input
);
-- u3:BUFG
-- port map(I=>Tem_Clk_DDR,
-- O=>Clk_DDR
-- );
process(Clk_DDR) begin
if rising_edge(Clk_DDR) then
if Cnt_DDRDIV=5 then
Cnt_DDRDIV<=0;
else
Cnt_DDRDIV<=Cnt_DDRDIV+1;
end if;
case Cnt_DDRDIV is
when 0 to 2 =>
Tem_Clk_DDR_DIV<='1';
when others =>
Tem_Clk_DDR_DIV<='0';
end case;
end if;
end process;
u4:BUFG
port map(I=>Tem_Clk_DDR_DIV,
O=>Clk_DDR_DIV
);
---------------------------------------------------------
gen_DPA:for I_Gen in 11 downto 0 generate
begin
Inst_DPA:DPA
port map(Clk_DDR=>Clk_DDR,
Clk_DDR_Div=>Clk_DDR_Div,
Cmd_Training=>Cmd_Training,
LVDS_IN_P=>LVDS_IN_P(I_Gen),
LVDS_IN_N=>LVDS_IN_N(I_Gen),
Training_Done=>Training_Done(I_Gen),
LVDS_Dout=>Tem_LVDS_OUT(I_Gen),
--LVDS_Clk=>
LVDS_Dlen_n=>LVDS_OUT_Dlen_n(I_Gen)
);
end generate;
--
end Behavioral;

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module register_option_spi(
input sys_clk_50M,
input sys_reset_n,
input data_miso_in,
output data_mosi_out,
output sck,
output ss_n ,
output spi_in_flag
);
reg [3:0] sersor_register_state;
parameter STATUS_INITIAL = 4'd0;
parameter STATUS_WRITE = 4'd1;
parameter STATUS_READ = 4'd2;
parameter STATUS_IDLE = 4'd3;
//<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>д,<EFBFBD><EFBFBD>(req:<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>sec<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ)
reg read_req;
//reg [8:0]read_sec;
reg write_req;
reg [8:0]write_sec;
wire [8:0]write_sec_sersor;
reg [8:0]write_sec_sersor_rr;
wire [15:0]write_data_sersor;
wire init_over ;
wire all_done ;
wire [8:0] write_sec_sersor_r;
wire write_over ;
wire read_over ;
wire [15:0] data_rec;
reg [15:0] write_data_sersor_r;
reg [15:0] data_rec_r;
assign data_in = data_rec_r;
always@(posedge sys_clk_50M or negedge sys_reset_n)
begin
if(!sys_reset_n)
begin
sersor_register_state <= 4'd0;
read_req <= 1'b0;
//read_sec <= 9'd0;
write_req <= 1'b0;
write_sec_sersor_rr <= 9'd0;
end
else
case(sersor_register_state)
0: //<EFBFBD>ȴ<EFBFBD>sersor_operation<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵ<EFBFBD>ָʾ<EFBFBD>źţ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ÿһ<EFBFBD><EFBFBD>״̬<EFBFBD><EFBFBD>ָʾ<EFBFBD>źţ<EFBFBD>
if(init_over==1'b1)
begin
sersor_register_state <= 4'd1;
end
else
begin
sersor_register_state <= 4'd0;
end
1:
begin
if(!all_done)
begin
sersor_register_state <= 4'd2;
write_sec_sersor_rr <= write_sec_sersor_r;
write_req <= 1'b1;
end
else
sersor_register_state <= 4'd1;
end
2:
if(write_over)
begin
sersor_register_state <= 4'd3;
write_sec_sersor_rr<= write_sec_sersor_r;
read_req <= 1'b1;
write_req<=1'b0;
end
else
begin
write_req <= 1'b1;
sersor_register_state <= 4'd2;
end
3:
if(read_over)
begin
sersor_register_state <= 4'd1;
read_req <= 1'b0;
end
else
begin
read_req <= 1'b1;
sersor_register_state <= 3;
end
default: begin
sersor_register_state <= 4'd1;
read_req <= 1'b0;
write_req <= 1'b0;
end
endcase
end
//wire ss_n;
//wire sck ;
wire spi_in;
//wire spi_in_flag;
//wire data_miso_in;
//wire data_mosi_out;
//wire write_over; //д<EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>ʶ
//wire read_over; //<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>ʶ
//wire all_done;
//wire write_req ;
//wire read_req ;
//wire sys_clk_50M ;
//wire sys_reset_n ;
assign write_sec_sersor_r = write_sec_sersor;
sensor_operation sensor_operation_inst(
.init_over(init_over),
.camera_clk(sys_clk_50M),
.rst_n(sys_reset_n),
.write_data_sersor(write_data_sersor),
.write_sec_sersor(write_sec_sersor),
.read_over(read_over),
.all_done(all_done)
);
//д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
spi spi_inst(
.clk ( sys_clk_50M ) ,
.rst_n ( sys_reset_n ) ,
.addr ( write_sec_sersor_rr ) ,
.data_in ( write_data_sersor_r) ,
.cmd_write ( write_req ) ,
.cmd_read ( read_req ) ,
.spi_in ( data_miso_in ) ,
.write_done ( write_over ) ,
.read_done ( read_over ) ,
.ss_n ( ss_n ) ,
.spi_out ( data_mosi_out ) ,
.sck ( sck ) ,
.spi_in_flag ( spi_in_flag ) ,
.dout ( data_rec )
);
//<EFBFBD><EFBFBD>д
always@(posedge sys_clk_50M)
begin
case(sersor_register_state)
STATUS_INITIAL:
begin
if(init_over) sersor_register_state <=STATUS_WRITE;
else sersor_register_state <= STATUS_INITIAL;
end
STATUS_WRITE:
begin
write_data_sersor_r <= write_data_sersor;
end
STATUS_READ:
begin
data_rec_r <= data_rec;
end
default:
begin
data_rec_r<=16'b0;
write_data_sersor_r <= 16'b0;
end
endcase
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:34:38 08/22/2017
// Design Name:
// Module Name: sensor_operation
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sensor_operation(
input camera_clk,
input rst_n,
input read_over,
output [15:0] write_data_sersor,
output [8:0] write_sec_sersor,
output init_over,
output all_done,
output reset_n
);
parameter POWER_OFF = 8'b0000_0001,
LOW_POWER_STANDBY = 8'b0000_0010,
STANGBY_1 = 8'b0000_0100,
STANGBY_2 = 8'b0000_1000,
IDLE = 8'b0001_0000,
RUNNING = 8'b0010_0000,
INTERMEDIATE_STANDBY = 8'b0100_0000;
parameter COUNT = 600; //Power up sequence count
reg [7:0] FSM_STATES;
reg [2:0]counta = 3'd0; //Enable clock management part 1(count)
reg [6:0] countd = 7'd0;
reg [15:0] write_data_sersor_r ;
reg [8:0] write_sec_sersor_r ;
reg all_done_r;
reg reset_n_r ;
reg [9:0] cnt_sersor;
reg init_over_r ;
reg [107:0] register[24:0];
assign write_data_sersor=write_data_sersor_r ;
assign write_sec_sersor = write_sec_sersor_r ;
assign all_done = all_done_r ;
assign reset_n = reset_n_r;
assign init_over= init_over_r;
always@(posedge camera_clk)
begin
if(!rst_n)
begin
cnt_sersor <= 0;
all_done_r<= 1'b0 ;
register[ 0] ={9'd41, 16'h085F} ;
register[ 1] ={9'd42, 16'h4110} ;
register[ 2] ={9'd43, 16'h0008} ;
register[ 3] ={9'd65, 16'h382B} ;
register[ 4] ={9'd66, 16'h53C8} ;
register[ 5] ={9'd67, 16'h0665} ;
register[ 6] ={9'd68, 16'h0085} ;
register[ 7] ={9'd69, 16'h0088} ;
register[ 8] ={9'd70, 16'h1111} ;
register[ 9] ={9'd72, 16'h0010} ;
register[ 10] ={9'd128,16'h4714} ;
register[ 11] ={9'd129,16'h8001} ;
register[ 12] ={9'd171,16'h1002} ;
register[ 13] ={9'd175,16'h0080} ;
register[ 14] ={9'd176,16'h00E6} ;
register[ 15] ={9'd177,16'h0400} ;
register[ 16] ={9'd192,16'h080C} ;
register[ 17] ={9'd194,16'h0224} ;
register[ 18] ={9'd197,16'h0306} ;
register[ 19] ={9'd204,16'h01E1} ;
register[ 20] ={9'd207,16'h0000} ;
register[ 21] ={9'd211,16'h0E49} ;
register[ 22] ={9'd215,16'h111F} ;
register[ 23] ={9'd216,16'h7F00} ;
register[ 24] ={9'd219,16'h0020} ;
register[ 25] ={9'd220,16'h3A28} ;
register[ 26] ={9'd221,16'h624D} ;
register[ 27] ={9'd222,16'h624D} ;
register[ 28] ={9'd224,16'h3E5E} ;
register[ 29] ={9'd227,16'h0000} ;
register[ 30] ={9'd250,16'h2081} ;
register[ 31] ={9'd384,16'hC800} ;
register[ 32] ={9'd385,16'hFB1F} ;
register[ 33] ={9'd386,16'hFB1F} ;
register[ 34] ={9'd387,16'hFB12} ;
register[ 35] ={9'd388,16'hF903} ;
register[ 36] ={9'd389,16'hF802} ;
register[ 37] ={9'd390,16'hF30F} ;
register[ 38] ={9'd391,16'hF30F} ;
register[ 39] ={9'd392,16'hF30F} ;
register[ 40] ={9'd393,16'hF30A} ;
register[ 41] ={9'd394,16'hF101} ;
register[ 42] ={9'd395,16'hF00A} ;
register[ 43] ={9'd396,16'hF24B} ;
register[ 44] ={9'd397,16'hF226} ;
register[ 45] ={9'd398,16'hF001} ;
register[ 46] ={9'd399,16'hF402} ;
register[ 47] ={9'd400,16'hF001} ;
register[ 48] ={9'd401,16'hF402} ;
register[ 49] ={9'd402,16'hF001} ;
register[ 50] ={9'd403,16'hF401} ;
register[ 51] ={9'd404,16'hF007} ;
register[ 52] ={9'd405,16'hF20F} ;
register[ 53] ={9'd406,16'hF20F} ;
register[ 54] ={9'd407,16'hF202} ;
register[ 55] ={9'd408,16'hF006} ;
register[ 56] ={9'd409,16'hEC02} ;
register[ 57] ={9'd410,16'hE801} ;
register[ 58] ={9'd411,16'hEC02} ;
register[ 59] ={9'd412,16'hE801} ;
register[ 60] ={9'd413,16'hEC02} ;
register[ 61] ={9'd414,16'hC801} ;
register[ 62] ={9'd415,16'hC800} ;
register[ 63] ={9'd416,16'hC800} ;
register[ 64] ={9'd417,16'hCC02} ;
register[ 65] ={9'd418,16'hC801} ;
register[ 66] ={9'd419,16'hCC02} ;
register[ 67] ={9'd420,16'hC801} ;
register[ 68] ={9'd421,16'hCC02} ;
register[ 69] ={9'd422,16'hC805} ;
register[ 70] ={9'd423,16'hC800} ;
register[ 71] ={9'd424,16'h0030} ;
register[ 72] ={9'd425,16'h207C} ;
register[ 73] ={9'd426,16'h2071} ;
register[ 74] ={9'd427,16'h0074} ;
register[ 75] ={9'd428,16'h107F} ;
register[ 76] ={9'd429,16'h1072} ;
register[ 77] ={9'd430,16'h1074} ;
register[ 78] ={9'd431,16'h0076} ;
register[ 79] ={9'd432,16'h0031} ;
register[ 80] ={9'd433,16'h21BB} ;
register[ 81] ={9'd434,16'h20B1} ;
register[ 82] ={9'd435,16'h20B1} ;
register[ 83] ={9'd436,16'h00B1} ;
register[ 84] ={9'd437,16'h10BF} ;
register[ 85] ={9'd438,16'h10B2} ;
register[ 86] ={9'd439,16'h10B4} ;
register[ 87] ={9'd440,16'h00B1} ;
register[ 88] ={9'd441,16'h0030} ;
register[ 89] ={9'd442,16'h0030} ;
register[ 90] ={9'd443,16'h217B} ;
register[ 91] ={9'd444,16'h2071} ;
register[ 92] ={9'd445,16'h2071} ;
register[ 93] ={9'd446,16'h0074} ;
register[ 94] ={9'd447,16'h107F} ;
register[ 95] ={9'd448,16'h1072} ;
register[ 96] ={9'd449,16'h1074} ;
register[ 97] ={9'd450,16'h0076} ;
register[ 98] ={9'd451,16'h0031} ;
register[ 99] ={9'd452,16'h20BB} ;
register[ 100] ={9'd453,16'h20B1} ;
register[ 101] ={9'd454,16'h20B1} ;
register[ 102] ={9'd455,16'h00B1} ;
register[ 103] ={9'd456,16'h10BF} ;
register[ 104] ={9'd457,16'h10B2} ;
register[ 105] ={9'd458,16'h10B4} ;
register[ 106] ={9'd459,16'h00B1} ;
register[ 107] ={9'd460,16'h0030} ;
end
else
begin
cnt_sersor <= cnt_sersor+1;
end
end
reg start_flag = 1'b1;
always@(posedge camera_clk)
begin
if(!rst_n)begin FSM_STATES<=POWER_OFF;countd <= 0 ;end
else begin
case(FSM_STATES)
POWER_OFF: //Power up sequence|NULL
begin
reset_n_r <= 1'b1;
if(cnt_sersor>COUNT)
begin
start_flag <= 1'b1;
init_over_r <= 1'b1;
FSM_STATES <= LOW_POWER_STANDBY;
end
end
LOW_POWER_STANDBY: //Enable clock management part 1|Power down sequence
begin
if(start_flag)
begin
case(counta)
3'd0:
begin
write_sec_sersor_r <= 9'd2;
write_data_sersor_r <= 16'h0000; //Monochrome sensor
if(read_over) counta <= counta+1;
end
3'd1:
begin
write_sec_sersor_r <= 9'd8;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
3'd2:
begin
write_sec_sersor_r <= 9'd16;
write_data_sersor_r <= 16'h0003;
if(read_over) counta <= counta+1;
end
3'd3:
begin
write_sec_sersor_r <= 9'd17;
write_data_sersor_r <= 16'h2113;
if(read_over) counta <= counta+1;
end
3'd4:
begin
write_sec_sersor_r <= 9'd20;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
3'd5:
begin
write_sec_sersor_r <= 9'd26;
write_data_sersor_r <= 16'h2280;
if(read_over) counta <= counta+1;
end
3'd6:
begin
write_sec_sersor_r <= 9'd27;
write_data_sersor_r <= 16'h3D2D;
if(read_over) counta <= counta+1;
end
3'd7:
begin
write_sec_sersor_r <= 9'd32;
write_data_sersor_r <= 16'h7004;
if(read_over) counta <= counta+1;
end
endcase
if(counta==7) begin FSM_STATES <= STANGBY_1; counta <=0; start_flag <= 1'b1;end
end
/////////////
else
begin
reset_n_r <= 1'b0;
init_over_r <= 1'b0;
start_flag<=0;
end
end
STANGBY_1: //Enable clock management part 2|Disable clock management part 1
begin
if(start_flag)
begin
case(counta)
3'd0:
begin
write_sec_sersor_r <= 9'd9;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
3'd1:
begin
write_sec_sersor_r <= 9'd32;
write_data_sersor_r <= 16'h7006;
if(read_over) counta <= counta+1;
end
3'd2:
begin
write_sec_sersor_r <= 9'd34;
write_data_sersor_r <= 16'h0001;
if(read_over) counta <= counta+1;
end
endcase
if(counta==3) begin FSM_STATES <=INTERMEDIATE_STANDBY; counta<=0; start_flag <= 1'b1;end
end
/////////////
else
begin
case(counta)
3'd0:
begin
write_sec_sersor_r <= 9'd8;
write_data_sersor_r <= 16'h0099;
if(read_over) counta <= counta+1;
end
3'd1:
begin
write_sec_sersor_r <= 9'd16;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
endcase
if(counta==2) begin FSM_STATES <= LOW_POWER_STANDBY; counta<=0;start_flag<=0; all_done_r <= 1;end
end
end
INTERMEDIATE_STANDBY: //Required Register uploaded|NULL
begin
if(countd<108)begin
if(read_over)begin
write_sec_sersor_r <= register[countd][24:16];
write_data_sersor_r <= register[countd][15:0];
countd <= countd+1;
end
end
else if(countd==108) begin FSM_STATES <= STANGBY_2;start_flag <= 1'b1;end
end
STANGBY_2: //Soft power up|Disable clock management part 2
begin
if(start_flag)
begin
case(counta)
3'd0:
begin
write_sec_sersor_r <= 9'd10;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
3'd1:
begin
write_sec_sersor_r <= 9'd32;
write_data_sersor_r <= 16'h7007;
if(read_over) counta <= counta+1;
end
3'd2:
begin
write_sec_sersor_r <= 9'd40;
write_data_sersor_r <= 16'h0003;
if(read_over) counta <= counta+1;
end
3'd3:
begin
write_sec_sersor_r <= 9'd42;
write_data_sersor_r <= 16'h4113;
if(read_over) counta <= counta+1;
end
3'd4:
begin
write_sec_sersor_r <= 9'd48;
write_data_sersor_r <= 16'h0001;
if(read_over) counta <= counta+1;
end
3'd5:
begin
write_sec_sersor_r <= 9'd64;
write_data_sersor_r <= 16'h0001;
if(read_over) counta <= counta+1;
end
3'd6:
begin
write_sec_sersor_r <= 9'd72;
write_data_sersor_r <= 16'h0017;
if(read_over) counta <= counta+1;
end
3'd7:
begin
write_sec_sersor_r <= 9'd112;
write_data_sersor_r <= 16'h0007;
if(read_over) counta <= counta+1;
end
endcase
if(counta==7) begin FSM_STATES <= IDLE;counta <=0;start_flag <= 1'b1; end
end
//////////
else
begin
case(counta)
3'd0:
begin
write_sec_sersor_r <= 9'd9;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
3'd1:
begin
write_sec_sersor_r <= 9'd32;
write_data_sersor_r <= 16'h7004;
if(read_over) counta <= counta+1;
end
3'd2:
begin
write_sec_sersor_r <= 9'd34;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
endcase
if(counta==3) begin FSM_STATES <= STANGBY_1; counta<=0;start_flag<=0; end
end
end
IDLE: //Enable sequence|Soft power down
begin
if(start_flag)
begin
case(counta)
3'd0:
begin
write_sec_sersor_r <= 9'd192;
write_data_sersor_r <= 16'h080D;
if(read_over) counta <= counta+1;
end
endcase
if(counta==1) begin FSM_STATES <= RUNNING; counta<=0;start_flag <= 1'b1;end
end
//////////////////////////////////////////////
else
begin
case(counta)
3'd0:
begin
write_sec_sersor_r <= 9'd10;
write_data_sersor_r <= 16'h9999;
if(read_over) counta <= counta+1;
end
3'd1:
begin
write_sec_sersor_r <= 9'd32;
write_data_sersor_r <= 16'h7006;
if(read_over) counta <= counta+1;
end
3'd2:
begin
write_sec_sersor_r <= 9'd40;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
3'd3:
begin
write_sec_sersor_r <= 9'd42;
write_data_sersor_r <= 16'h4110;
if(read_over) counta <= counta+1;
end
3'd4:
begin
write_sec_sersor_r <= 9'd48;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
3'd5:
begin
write_sec_sersor_r <= 9'd64;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
3'd6:
begin
write_sec_sersor_r <= 9'd72;
write_data_sersor_r <= 16'h0010;
if(read_over) counta <= counta+1;
end
3'd7:
begin
write_sec_sersor_r <= 9'd112;
write_data_sersor_r <= 16'h0000;
if(read_over) counta <= counta+1;
end
endcase
if(counta==7) begin FSM_STATES <= STANGBY_2;counta<=0;start_flag<=0;end
end
end
RUNNING: // NULL|Disable squence
begin
if(start_flag) start_flag<=0;
else
begin
case(counta)
3'd0:
begin
write_sec_sersor_r <= 9'd192;
write_data_sersor_r <= 16'h080C;
if(read_over) counta <= counta+1;
end
endcase
if(counta==1) begin FSM_STATES<=IDLE; counta<=0;start_flag<=0;end
end
end
default: //set IDLE
begin
write_sec_sersor_r <= 9'd192;
write_data_sersor_r <= 16'h080D;
end
endcase
end
end
endmodule

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module spi(
clk ,
rst_n ,
addr ,
data_in ,
cmd_write ,
cmd_read ,
spi_in ,
write_done ,
read_done ,
ss_n ,
spi_out ,
sck ,
spi_in_flag ,
dout
);
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
parameter DATA_W = 16;
parameter ADDR_W = 9 ;
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źŶ<EFBFBD><EFBFBD><EFBFBD>
input clk ;
input rst_n ;
input[DATA_W-1:0] data_in ;
input[ADDR_W-1:0] addr ;
input cmd_write ;
input cmd_read ;
input spi_in ;
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źŶ<EFBFBD><EFBFBD><EFBFBD>
output[DATA_W-1:0] dout ;
output write_done ;
output read_done ;
output ss_n ;
output spi_out ;
output sck ;
output spi_in_flag ;
//<EFBFBD>м<EFBFBD><EFBFBD>ź<EFBFBD>reg<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
reg[DATA_W-1:0] data_r ;
reg[ADDR_W:0] addr_r ;
reg cmd_write_r ;
reg cmd_write_rr ;
reg cmd_read_r ;
reg cmd_read_rr ;
reg[4:0] cnt_spi ;
reg[4:0] i ;
reg[DATA_W-1:0] dataout_r ;
reg ss_n_r ;
reg sck_r ;
reg spi_out_r ;
reg write_done_r ;
reg read_done_r ;
reg spi_in_flag_r;
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD>SS_N<EFBFBD>ź<EFBFBD>
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
cmd_read_rr <= 1'b0 ;
cmd_read_r <= 1'b0 ;
cmd_write_rr<= 1'b0 ;
cmd_write_r <= 1'b0 ;
cnt_spi <= 5'd0 ;
i <= 5'd0 ;
ss_n_r <= 1'b1 ;
end
else begin
cmd_read_r <= cmd_read ;
cmd_read_rr <= cmd_read_r ;
cmd_write_r <= cmd_write ;
cmd_write_rr <= cmd_write_r ;
if(i==5'd30&&cnt_spi==5'd3)begin
i <= 5'd0 ;
end
if(cmd_write_rr==1'b1||cmd_read_rr==1'b1)begin
if(cnt_spi==5'd24)begin
cnt_spi <=5'd0 ;
i <= i+ 1 ;
end
else if(i==5'd30&&cnt_spi==5'd3)begin
cnt_spi <= 5'd0 ;
end
else begin
cnt_spi <= cnt_spi + 1 ;
end
if(i<5'd28)begin
ss_n_r <= 1'b0 ;
end
if(i==5'd28)begin
ss_n_r <= 1'b1 ;
end
end
else begin
ss_n_r <= 1'b1 ;
end
end
end
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD>SCK<EFBFBD>ź<EFBFBD>
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
sck_r <= 1'b0 ;
end
else begin
if(i>0 && i < 5'd27)begin
if(cnt_spi==0 || cnt_spi == 5'd12)begin
sck_r <= ~sck_r ;
end
end
else begin
sck_r <= 1'd0 ;
end
end
end
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD>spi_out<EFBFBD>ź<EFBFBD>
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
spi_out_r <= 1'b0 ;
dataout_r <= 16'd0;
write_done_r <= 1'b0;
read_done_r <= 1'b0;
spi_in_flag_r <= 1'b0;
end
else begin
// if(i==5'd0 && cnt_spi==5'd0)begin
// dataout_r <= 16'd0 ;
// end
if(cmd_write_rr==1'b1)begin
data_r <= data_in ;
addr_r <= {addr,1'b1} ;
// if((i>=5'd0&&i<5'd10)&&cnt_spi== 5'd12)begin
// spi_out_r <= addr_r[9-i] ;
// end
if(i==5'd0&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd1&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd2&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd3&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd4&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd5&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd6&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd7&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd8&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
if(i==5'd9&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
//????
if(i==5'd10&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd11&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd12&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd13&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd14&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd15&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd16&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd17&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd18&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd19&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd20&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd21&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd22&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd23&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd10&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd10&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd24&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd25&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
if(i==5'd26&&cnt_spi==5'd12)begin
spi_out_r <= 1'b0 ;
end
if(i==5'd30&&cnt_spi==5'd0)begin
write_done_r<=1'b1;
end
else begin
write_done_r<= 1'b0;
end
end
else if(cmd_read_rr==1'b1)begin //<EFBFBD><EFBFBD>ͬʱ<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD>Ч<EFBFBD><EFBFBD>ֻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
addr_r <={addr,1'b0};
if(i==5'd0&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd1&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd2&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd3&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd4&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd5&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd6&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd7&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd8&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd9&& cnt_spi== 5'd12)begin
spi_out_r <= addr_r[9-i] ;
end
else if(i==5'd11&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd12&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd13&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd14&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd15&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
if(i==5'd16&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd17&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd18&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd19&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd20&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd21&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd22&&cnt_spi==5'd12)begin
spi_out_r <= data_r[25-i];
end
else if(i==5'd23&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd24&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd25&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd26&&cnt_spi==5'd12)begin
dataout_r[26-i] <= spi_in;
end
else if(i==5'd29 && cnt_spi==5'd24)begin
read_done_r<=1'b1;
end
else begin
read_done_r<=1'b0 ;
end
end
else begin
spi_out_r <= 1'b0 ;
end
end
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
spi_in_flag_r <= 1'b0 ;
end
else begin
if(cmd_read_rr==1'b1)begin
if(i==5'd11 && cnt_spi==5'd0)begin
spi_in_flag_r <= 1'b1 ;
end
else begin spi_in_flag_r <= 1'b0 ;end
end
else begin
spi_in_flag_r <= 1'b0 ;
end
end
end
assign dout = dataout_r ;
assign ss_n = ss_n_r ;
assign sck = sck_r ;
assign spi_out=spi_out_r ;
assign spi_in_flag=spi_in_flag_r ;
assign write_done=write_done_r ;
assign read_done= read_done_r ;
endmodule

116
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:05:54 08/22/2017
// Design Name: spi
// Module Name: D:/work/ADC Snap/ON_sensor/ON_sensor/test_spi.v
// Project Name: ON_sensor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module write_read_spi;
// Inputs
reg clk;
reg rst_n;
reg spi_in;
// Outputs
wire spi_in_flag;
wire ss_n;
wire spi_out;
wire sck;
//????????ns???????????
parameter CYCLE = 20;
//???????????3?????????
parameter RST_TIME = 3 ;
// Instantiate the Unit Under Test (UUT)
register_option_spi uut (
.sys_clk_50M (clk) ,
.sys_reset_n (rst_n) ,
.data_miso_in (spi_in) ,
.ss_n (ss_n) ,
.data_mosi_out (spi_out) ,
.sck (sck) ,
.spi_in_flag (spi_in_flag)
);
//<EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>50M
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD>ź<EFBFBD>
initial begin
rst_n = 1;
#10;
rst_n = 0;
#(CYCLE*RST_TIME);
rst_n = 1;
end
//<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>din0<EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD>ʽ
initial begin
#1;
repeat(300) begin
wait(spi_in_flag==1'b1)
spi_in = 1 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 1 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 1 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 1 ;
#(25*CYCLE) ;
spi_in = 0 ; //1000 0100 0010 0001
end
end
endmodule

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/others/tb_training.vhd Normal file
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:54 08/15/2017
-- Design Name:
-- Module Name: D:/li/gesens/out/ddr2/full_ddr2_20170812_right_isim/tb_training.vhd
-- Project Name: ddr_2_place
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IND_B
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_training IS
END tb_training;
ARCHITECTURE behavior OF tb_training IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IND_B
PORT(
Clk200m : IN std_logic;
CLK200M_Rst : IN std_logic;
Clk_DDR : IN std_logic;
Clk_DDR_Div : IN std_logic;
Cmd_Training : IN std_logic;
LVDS_IN_P : IN std_logic_vector(31 downto 0);
LVDS_IN_N : IN std_logic_vector(31 downto 0);
LVDS_OUT1 : OUT std_logic_vector(191 downto 0);
LVDS_OUT2 : OUT std_logic_vector(191 downto 0)
);
END COMPONENT;
--Inputs
signal Clk200m : std_logic := '0';
signal CLK200M_Rst : std_logic := '0';
signal Clk_DDR : std_logic := '0';
signal Clk_DDR_Div : std_logic := '0';
signal Cmd_Training : std_logic := '0';
signal LVDS_IN_P : std_logic_vector(31 downto 0) := (others => '0');
signal LVDS_IN_N : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal LVDS_OUT1 : std_logic_vector(191 downto 0);
signal LVDS_OUT2 : std_logic_vector(191 downto 0);
-- Clock period definitions
constant Clk200m_period : time := 5 ns;
constant Clk_DDR_period : time := 4 ns;
constant Clk_DDR_Div_period : time := 24 ns;
signal cnt12: integer range 0 to 15;
signal Clk_DDR_mux : std_logic ;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IND_B PORT MAP (
Clk200m => Clk200m,
CLK200M_Rst => CLK200M_Rst,
Clk_DDR => Clk_DDR,
Clk_DDR_Div => Clk_DDR_Div,
Cmd_Training => Cmd_Training,
LVDS_IN_P => LVDS_IN_P,
LVDS_IN_N => LVDS_IN_N,
LVDS_OUT1 => LVDS_OUT1,
LVDS_OUT2 => LVDS_OUT2
);
-- Clock process definitions
Clk200m_process :process
begin
Clk200m <= '0';
wait for Clk200m_period/2;
Clk200m <= '1';
wait for Clk200m_period/2;
end process;
CLK200M_Rst_process :process
begin
CLK200M_Rst <= '1';
wait for 1 us;
CLK200M_Rst <= '0';
wait ;
end process;
process
begin
Cmd_Training <= '1';
wait for 2 us;
Cmd_Training <= '0';
wait for 100 us;
Cmd_Training <= '1';
wait for 100 us;
Cmd_Training <= '0';
wait for 100 us;
Cmd_Training <= '1';
wait;
end process;
Clk_DDR_process :process
begin
Clk_DDR <= '0';
wait for Clk_DDR_period/2;
Clk_DDR <= '1';
wait for Clk_DDR_period/2;
end process;
Clk_DDR_Div_process :process
begin
Clk_DDR_Div <= '0';
wait for Clk_DDR_Div_period/2;
Clk_DDR_Div <= '1';
wait for Clk_DDR_Div_period/2;
end process;
process
begin
Clk_DDR_mux <= '0';
wait for 1 ns;
Clk_DDR_mux <= '1';
wait for 1 ns;
end process;
process(Clk_DDR_mux) begin
if rising_edge(Clk_DDR_mux) then
if cnt12=11 then
cnt12<=0;
else
cnt12<=cnt12+1;
end if;
end if;
end process;
process(Clk_DDR_mux) begin
if rising_edge(Clk_DDR_mux) then
case cnt12 is
when 0 =>
LVDS_IN_P<=x"ffffffff";
LVDS_IN_N<=x"00000000";
when 1 =>
LVDS_IN_P<=x"00000000";
LVDS_IN_N<=x"ffffffff";
when 2 =>
LVDS_IN_P<=x"00000000";
LVDS_IN_N<=x"ffffffff";
when 3 =>
LVDS_IN_P<=x"ffffffff";
LVDS_IN_N<=x"00000000";
when 4 =>
LVDS_IN_P<=x"ffffffff";
LVDS_IN_N<=x"00000000";
when 5 =>
LVDS_IN_P<=x"00000000";
LVDS_IN_N<=x"ffffffff";
when 6 =>
LVDS_IN_P<=x"00000000";
LVDS_IN_N<=x"ffffffff";
when 7 =>
LVDS_IN_P<=x"00000000";
LVDS_IN_N<=x"ffffffff";
when 8 =>
LVDS_IN_P<=x"ffffffff";
LVDS_IN_N<=x"00000000";
when 9 =>
LVDS_IN_P<=x"ffffffff";
LVDS_IN_N<=x"00000000";
when 10 =>
LVDS_IN_P<=x"ffffffff";
LVDS_IN_N<=x"00000000";
when 11 =>
LVDS_IN_P<=x"00000000";
LVDS_IN_N<=x"ffffffff";
when others =>
null;
end case;
end if;
end process;
END;

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module usb_controller(
usb_clk,
USB_DATA,
data_in,
data_pulse,
nframe,
send_out
);
input usb_clk ;
output USB_DATA;
input [15:0]data_in ;
output data_pulse ;
input nframe ;
input send_out ;
reg [15:0]USB_DATA ;
reg data_pulse ;
reg [9:0]counter ;
reg flag_counter ;
reg [3:0]main_state = power_up ;
parameter
power_up = 4'b0000 ,
usb_idle = 4'b0001 ,
usb_EP6 = 4'b0010 ,
usb_send = 4'b0011 ,
usb_delay1= 4'b0100 ,
usb_delay2= 4'b0101 ;
always @ ( posedge nframe or posedge usb_clk )
begin
if ( nframe == 1 )
begin
counter <= 0 ;
end
else
if ( flag_counter )
begin
counter <= counter + 1 ;
end
else
begin
counter <= 0 ;
end
end
always @ ( posedge nframe or posedge usb_clk )
begin
if ( nframe )
begin
main_state <= power_up ;
flag_counter <= 0 ;
data_pulse <= 0 ;
end
else
begin
case ( main_state )
power_up :
begin
main_state <= power_up ;
flag_counter <= 0 ;
data_pulse <= 0 ;
end
usb_idle :
begin
flag_counter <= 0 ;
data_pulse <= 0 ;
if ( send_out )
main_state <= usb_send ;
end
usb_send :
begin
main_state <= usb_delay1 ;
flag_counter <= 0 ;
data_pulse <= 1 ;
end
usb_delay1 :
begin
main_state <= usb_delay2 ;
flag_counter <= 0 ;
end
usb_delay2 :
begin
main_state <= usb_EP6 ;
flag_counter <= 1 ;
end
usb_EP6 :
begin
USB_DATA <= data_in ;
if ( counter == 256 )
begin
main_state <= usb_idle ;
end
else
if ( counter == 253 )
begin
data_pulse <= 0 ;
end
else
begin
//写到SD卡
end
end
default :
begin
flag_counter <= 0 ;
main_state <= power_up ;
USB_DATA <= 0 ;
end
endcase
end
end
endmodule

11
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/20171106.cfi Normal file
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# PROMGEN: Xilinx Prom Generator P.20131013
# Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
SOFTWARE_VERSION P.20131013
DATE 11/06/2017 - 07:13
SOURCE D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\20171106.mcs
DEVICE 16384K
DATA_WIDTH 1
FILL_DATA 0xFF
SIGNATURE 0xE8C186BD
START_ADDRESS 0x00000000 END_ADDRESS 0x0016A89F DIRECTION_UP "D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/main.bit" 6slx45csg324

92834
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/20171106.mcs Normal file
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File diff suppressed because it is too large Load Diff

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/20171106.prm Normal file
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@ -0,0 +1,17 @@
PROMGEN: Xilinx Prom Generator P.20131013
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
promgen -w -p mcs -c FF -o D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree//20171106 -s 16384 -u 0000 D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/main.bit -spi
PROM D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\20171106.prm map: Mon Nov 06 07:13:51 2017
Calculating PROM checksum with fill value ff
Format Mcs86 (32-bit)
Size 16384K
PROM start 0000:0000
PROM end 00ff:ffff
PROM checksum e8c186bd
Addr1 Addr2 Date File(s)
0000:0000 0016:a89f Nov 06 07:08:23 2017 D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/main.bit

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work

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:53:25 09/05/2017
// Design Name:
// Module Name: CMOS_Command
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CMOS_Command(
clk_input,spi_idle_feedback,reset,
data_write_spi,command_address_spi,execute_pulse_spi,
da_ini_pa_in,cd_ad_ini_pa_in,ini_reqeuest,ini_lah,
da_usb_in,usb_request,usb_empty,
rd_fb_cd,rd_fb_da,rd_fb_lah,
fd_to_usb_da,fd_to_usb_cd_ad,fifo_fd_en
);
input clk_input ;
input spi_idle_feedback,reset;
//////////////////////////////////////////////////////
output [15:0]data_write_spi;
output [9:0]command_address_spi;
output execute_pulse_spi;
reg [15:0]data_write_spi;
reg [9:0]command_address_spi;
reg execute_pulse_spi;
//////////////////////////////////////////////////////
input [15:0]da_ini_pa_in;
input [15:0]cd_ad_ini_pa_in;
input ini_lah ;
output ini_reqeuest;
reg ini_reqeuest;
//////////////////////////////////////////////////////
input [15:0]da_usb_in;
input usb_lah ;
input usb_empty ;
output usb_request ;
reg usb_request ;
/////////////////////////////////////////////////////
input [9:0]rd_fb_cd;
input [15:0]rd_fb_da;
input rd_fb_lah;
output [15:0]fd_to_usb_da;
output [15:0]fd_to_usb_cd_ad;
reg [15:0]fd_to_usb_da;
reg [15:0]fd_to_usb_cd_ad;
reg fifo_fd_en;
///////////////////////////////////////////////////
parameter
power_up = 6'b000000 ,
command_idle = 6'b000001 ,
cmose_interface_command = 6'b000010 ,
usb_command = 6'b000100 ,
command_busy = 6'b001000 ;
reg [5:0]main_state ;
always @ ( posedge clk_input or posedge reset )
begin
if ( reset )
begin
main_state <= power_up ;
end
else
begin
case ( main_state )
power_up :
begin
if ( spi_idle_feedback )
begin
main_state <= command_idle ;
end
end
command_idle :
begin
if ( usb_lah )
begin
main_state <= usb_command ;
end
end
end
end
endmodule

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MODULE CMOS_Interface

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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan6" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
</sheet>
</drawing>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/CMOS_Interface.schlog Normal file
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vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/CMOS_RESET.v -lang verilog -prj UAV_CMOS -o CMOS_RESET.spl -module CMOS_RESET -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l CMOS_RESET.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/CMOS_RESET.sym
vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/CMOS_RESET.v -lang verilog -prj UAV_CMOS -o CMOS_RESET.spl -module CMOS_RESET -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l CMOS_RESET.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/CMOS_RESET.sym

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/CMOS_RESET.lso Normal file
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work

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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="CMOS_RESET">
<symboltype>BLOCK</symboltype>
<timestamp>2017-9-16T2:12:7</timestamp>
<attr value="CMOS_RESET" name="VeriModel" />
<pin polarity="Input" x="0" y="-160" name="clk_input" />
<pin polarity="Input" x="0" y="-96" name="request_reset" />
<pin polarity="Input" x="0" y="-32" name="PLL_Lock" />
<pin polarity="Output" x="544" y="-32" name="reset_internal_module" />
<pin polarity="Output" x="544" y="-160" name="cmos_reset" />
<graph>
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk_input" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin request_reset" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin PLL_Lock" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<rect width="416" x="64" y="-192" height="192" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-32" type="pin reset_internal_module" />
<line x2="544" y1="-32" y2="-32" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-160" type="pin cmos_reset" />
<line x2="544" y1="-160" y2="-160" x1="480" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="268" y="-200" type="symbol" />
</graph>
</symbol>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/CMOS_RESET.symlog Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:48:40 09/16/2017
// Design Name:
// Module Name: CMOS_RESET
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CMOS_RESET(
clk_input,
cmos_reset,
request_reset,
PLL_Lock,
reset_internal_module
);
input clk_input ;
input request_reset;
input PLL_Lock ;
output reset_internal_module;
output cmos_reset;
reg cmos_reset = 0;
reg reset_internal_module = 0;
reg [14:0]reset_counter;
reg reset_flag1;
reg reset_flag2;
always @ ( posedge clk_input )
begin
reset_flag1 <= cmos_reset ;
reset_flag2 <= reset_flag1;
reset_internal_module <= (reset_flag1) && (~reset_flag2);
end
always @ ( posedge clk_input )
begin
if ( request_reset )
begin
cmos_reset <= 0 ;
reset_counter <= 0 ;
end
else
if ( reset_counter[14] )
begin
cmos_reset <= 1 ;
end
else
begin
reset_counter <= reset_counter + PLL_Lock ;
end
end
endmodule

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/FPGA_Command_Decoder.cmd_log Normal file
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vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/FPGA_Command_Decoder.v -lang verilog -prj UAV_CMOS -o FPGA_Command_Decoder.spl -module FPGA_Command_Decoder -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l FPGA_Command_Decoder.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/FPGA_Command_Decoder.sym
vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/FPGA_Command_Decoder.v -lang verilog -prj UAV_CMOS -o FPGA_Command_Decoder.spl -module FPGA_Command_Decoder -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l FPGA_Command_Decoder.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/FPGA_Command_Decoder.sym
vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/FPGA_Command_Decoder.v -lang verilog -prj UAV_CMOS -o FPGA_Command_Decoder.spl -module FPGA_Command_Decoder -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6 FPGA_Command_Decoder.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/FPGA_Command_Decoder.sym

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work

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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="FPGA_Command_Decoder">
<symboltype>BLOCK</symboltype>
<timestamp>2017-11-3T11:23:43</timestamp>
<attr value="FPGA_Command_Decoder" name="VeriModel" />
<pin polarity="Input" x="0" y="-160" name="clk" />
<pin polarity="Input" x="0" y="-96" name="command_latch" />
<pin polarity="Input" x="0" y="-32" name="command_data(7:0)" />
<pin polarity="Output" x="560" y="-160" name="request_reset_signal" />
<pin polarity="Output" x="560" y="32" name="request_nframe_signal" />
<pin polarity="Output" x="560" y="-96" name="usb_output" />
<pin polarity="Output" x="560" y="-32" name="sd_output" />
<graph>
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="280" y="-200" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin command_latch" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin command_data(7:0)" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="488" y="-160" type="pin request_reset_signal" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="488" y="32" type="pin request_nframe_signal" />
<line x2="560" y1="32" y2="32" x1="496" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="560" y1="-160" y2="-160" x1="496" />
<rect width="432" x="64" y="-192" height="264" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="488" y="-96" type="pin usb_output" />
<line x2="560" y1="-96" y2="-96" x1="496" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="488" y="-32" type="pin sd_output" />
<line x2="560" y1="-32" y2="-32" x1="496" />
</graph>
</symbol>

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:52:18 09/22/2017
// Design Name:
// Module Name: FPGA_Command_Decoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPGA_Command_Decoder(
clk,command_latch,command_data,request_reset_signal,request_nframe_signal,usb_output,sd_output
);
input clk ;
input command_latch ;
input [7:0]command_data ;
output request_nframe_signal;
output request_reset_signal;
output usb_output ;
output sd_output ;
reg request_reset_signal ;
reg request_nframe_signal ;
reg reset_flag ;
reg nframe_flag ;
reg usb_flag ;
reg sd_flag ;
reg usb_output ;
reg sd_output ;
reg reset_flag_falling_buf1;
reg reset_flag_falling_buf2;
reg nframe_flag_falling_buf1;
reg nframe_flag_falling_buf2;
reg usd_flag_falling_buf1 ;
reg usd_flag_falling_buf2 ;
reg sd_flag_falling_buf1 ;
reg sd_flag_falling_buf2 ;
reg [7:0]command_data_buf ;
always @ ( posedge clk )
begin
if ( command_latch )
begin
command_data_buf <= command_data ;
end
else
begin
if ( command_data_buf == 8'b10101010 )
begin
reset_flag <= 1 ;
command_data_buf <= 0 ;
end
else
if ( command_data_buf == 8'b01010101 )
begin
command_data_buf <= 0 ;
nframe_flag <= 1 ;
end
else
if ( command_data_buf == 8'b01011010 )
begin
usb_flag <= 1 ;
command_data_buf <= 0 ;
end
else
if ( command_data_buf == 8'b10100101 )
begin
command_data_buf <= 0 ;
sd_flag <= 1 ;
end
else
begin
reset_flag <= 0 ;
nframe_flag <= 0 ;
sd_flag <= 0 ;
usb_flag <= 0 ;
end
end
end
always @ ( posedge clk )
begin
reset_flag_falling_buf1 <= reset_flag ;
reset_flag_falling_buf2 <= reset_flag_falling_buf1 ;
request_reset_signal <= ( reset_flag_falling_buf2 ) && ( ~reset_flag_falling_buf1 ) ;
nframe_flag_falling_buf1 <= nframe_flag ;
nframe_flag_falling_buf2 <= nframe_flag_falling_buf1 ;
request_nframe_signal <= ( nframe_flag_falling_buf2 ) && ( ~nframe_flag_falling_buf1 ) ;
usd_flag_falling_buf1 <= usb_flag ;
usd_flag_falling_buf2 <= usd_flag_falling_buf1 ;
usb_output <= ( usd_flag_falling_buf2 ) && ( ~usd_flag_falling_buf1 ) ;
sd_flag_falling_buf1 <= sd_flag ;
sd_flag_falling_buf2 <= sd_flag_falling_buf1 ;
sd_output <= ( sd_flag_falling_buf2 ) && ( ~sd_flag_falling_buf1 ) ;
end
endmodule

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/LED_Working.cmd_log Normal file
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vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/LED_Working.v -lang verilog -prj UAV_CMOS -o LED_Working.spl -module LED_Working -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l LED_Working.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/LED_Working.sym
vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/LED_Working.v -lang verilog -prj UAV_CMOS -o LED_Working.spl -module LED_Working -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l LED_Working.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/LED_Working.sym

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/LED_Working.lso Normal file
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work

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/LED_Working.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="LED_Working">
<symboltype>BLOCK</symboltype>
<timestamp>2017-9-15T14:25:2</timestamp>
<attr value="LED_Working" name="VeriModel" />
<pin polarity="Input" x="0" y="-32" name="clk_input" />
<pin polarity="Output" x="384" y="-32" name="LED" />
<graph>
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-72" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin clk_input" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin LED" />
<rect width="256" x="64" y="-64" height="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</graph>
</symbol>

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:29:03 09/15/2017
// Design Name:
// Module Name: LED_Working
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LED_Working( clk_input,LED );
input clk_input ;
output LED ;
reg LED ;
reg [23:0]counter ;
always @ ( posedge clk_input )
begin
if ( counter[23] == 1 )
begin
LED <= ~LED ;
counter <= 0 ;
end
else
begin
counter <= counter + 1 ;
end
end
endmodule

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/LVDS_IDDR.cmd_log Normal file
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@ -0,0 +1,2 @@
sch2hdl -sympath D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/ipcore_dir -intstyle ise -family spartan6l -verilog LVDS_IDDR_drc.vf -w D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/LVDS_IDDR.sch
sch2sym -intstyle ise -family spartan6l -refsym LVDS_IDDR D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/LVDS_IDDR.sch D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/LVDS_IDDR.sym

1
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/LVDS_IDDR.jhd Normal file
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MODULE LVDS_IDDR

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/LVDS_IDDR.sch Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan6" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="XLXN_5" />
<signal name="XLXN_6" />
<signal name="XLXN_7" />
<signal name="XLXN_8" />
<signal name="XLXN_9" />
<signal name="XLXN_10" />
<signal name="XLXN_11" />
<signal name="XLXN_12" />
<signal name="XLXN_13" />
<signal name="XLXN_14" />
<signal name="LVDS_Channel1" />
<signal name="LVDS_Channel2" />
<signal name="LVDS_Channel3" />
<signal name="CMOS_CLK" />
<signal name="CMOS_CLK_INV" />
<signal name="XLXN_32" />
<signal name="XLXN_34" />
<signal name="XLXN_36" />
<signal name="XLXN_38" />
<signal name="XLXN_40" />
<signal name="XLXN_43" />
<signal name="Channel_0_P" />
<signal name="Channel_0_N" />
<signal name="Channel_1_P" />
<signal name="Channel_1_N" />
<signal name="Channel_2_P" />
<signal name="Channel_2_N" />
<signal name="Channel_3_P" />
<signal name="Channel_3_N" />
<signal name="Sync_P" />
<signal name="Sync_N" />
<signal name="XLXN_47" />
<signal name="LVDS_Channel0" />
<signal name="XLXN_49" />
<signal name="LVDS_Sync" />
<port polarity="Input" name="LVDS_Channel1" />
<port polarity="Input" name="LVDS_Channel2" />
<port polarity="Input" name="LVDS_Channel3" />
<port polarity="Input" name="CMOS_CLK" />
<port polarity="Input" name="CMOS_CLK_INV" />
<port polarity="Output" name="Channel_0_P" />
<port polarity="Output" name="Channel_0_N" />
<port polarity="Output" name="Channel_1_P" />
<port polarity="Output" name="Channel_1_N" />
<port polarity="Output" name="Channel_2_P" />
<port polarity="Output" name="Channel_2_N" />
<port polarity="Output" name="Channel_3_P" />
<port polarity="Output" name="Channel_3_N" />
<port polarity="Output" name="Sync_P" />
<port polarity="Output" name="Sync_N" />
<port polarity="Input" name="LVDS_Channel0" />
<port polarity="Input" name="LVDS_Sync" />
<blockdef name="iddr2">
<timestamp>2000-1-1T10:10:10</timestamp>
<rect width="192" x="64" y="-304" height="392" />
<line x2="0" y1="-128" y2="-128" x1="64" />
<line x2="0" y1="64" y2="64" x1="64" />
<line x2="0" y1="0" y2="0" x1="64" />
<line x2="0" y1="-192" y2="-192" x1="64" />
<line x2="0" y1="-256" y2="-256" x1="64" />
<line x2="320" y1="-192" y2="-192" x1="256" />
<line x2="320" y1="-32" y2="-32" x1="256" />
<line x2="0" y1="-64" y2="-64" x1="64" />
</blockdef>
<blockdef name="fd">
<timestamp>2000-1-1T10:10:10</timestamp>
<rect width="256" x="64" y="-320" height="256" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="320" y1="-256" y2="-256" x1="384" />
<line x2="64" y1="-128" y2="-144" x1="80" />
<line x2="80" y1="-112" y2="-128" x1="64" />
</blockdef>
<blockdef name="gnd">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-96" x1="64" />
<line x2="52" y1="-48" y2="-48" x1="76" />
<line x2="60" y1="-32" y2="-32" x1="68" />
<line x2="40" y1="-64" y2="-64" x1="88" />
<line x2="64" y1="-64" y2="-80" x1="64" />
<line x2="64" y1="-128" y2="-96" x1="64" />
</blockdef>
<blockdef name="vcc">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-64" x1="64" />
<line x2="64" y1="0" y2="-32" x1="64" />
<line x2="32" y1="-64" y2="-64" x1="96" />
</blockdef>
<blockdef name="iodelay2">
<timestamp>2009-3-13T20:26:47</timestamp>
<rect width="256" x="64" y="-640" height="640" />
<line x2="0" y1="-608" y2="-608" x1="64" />
<line x2="0" y1="-544" y2="-544" x1="64" />
<line x2="0" y1="-480" y2="-480" x1="64" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-608" y2="-608" x1="320" />
<line x2="384" y1="-464" y2="-464" x1="320" />
<line x2="384" y1="-320" y2="-320" x1="320" />
<line x2="384" y1="-176" y2="-176" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef>
<block symbolname="fd" name="XLXI_180">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_5" name="D" />
<blockpin signalname="Channel_0_P" name="Q" />
</block>
<block symbolname="fd" name="XLXI_181">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_6" name="D" />
<blockpin signalname="Channel_0_N" name="Q" />
</block>
<block symbolname="fd" name="XLXI_182">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_7" name="D" />
<blockpin signalname="Channel_1_P" name="Q" />
</block>
<block symbolname="fd" name="XLXI_183">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_8" name="D" />
<blockpin signalname="Channel_1_N" name="Q" />
</block>
<block symbolname="fd" name="XLXI_184">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_10" name="D" />
<blockpin signalname="Channel_2_P" name="Q" />
</block>
<block symbolname="fd" name="XLXI_185">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_9" name="D" />
<blockpin signalname="Channel_2_N" name="Q" />
</block>
<block symbolname="fd" name="XLXI_186">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_12" name="D" />
<blockpin signalname="Channel_3_P" name="Q" />
</block>
<block symbolname="fd" name="XLXI_187">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_11" name="D" />
<blockpin signalname="Channel_3_N" name="Q" />
</block>
<block symbolname="fd" name="XLXI_188">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_14" name="D" />
<blockpin signalname="Sync_P" name="Q" />
</block>
<block symbolname="fd" name="XLXI_189">
<blockpin signalname="CMOS_CLK" name="C" />
<blockpin signalname="XLXN_13" name="D" />
<blockpin signalname="Sync_N" name="Q" />
</block>
<block symbolname="iddr2" name="XLXI_200">
<blockpin signalname="XLXN_47" name="D" />
<blockpin signalname="CMOS_CLK" name="C0" />
<blockpin signalname="CMOS_CLK_INV" name="C1" />
<blockpin signalname="XLXN_43" name="CE" />
<blockpin signalname="XLXN_32" name="R" />
<blockpin signalname="XLXN_32" name="S" />
<blockpin signalname="XLXN_5" name="Q0" />
<blockpin signalname="XLXN_6" name="Q1" />
</block>
<block symbolname="iddr2" name="XLXI_201">
<blockpin signalname="LVDS_Channel1" name="D" />
<blockpin signalname="CMOS_CLK" name="C0" />
<blockpin signalname="CMOS_CLK_INV" name="C1" />
<blockpin signalname="XLXN_43" name="CE" />
<blockpin signalname="XLXN_34" name="R" />
<blockpin signalname="XLXN_34" name="S" />
<blockpin signalname="XLXN_7" name="Q0" />
<blockpin signalname="XLXN_8" name="Q1" />
</block>
<block symbolname="iddr2" name="XLXI_202">
<blockpin signalname="LVDS_Channel2" name="D" />
<blockpin signalname="CMOS_CLK" name="C0" />
<blockpin signalname="CMOS_CLK_INV" name="C1" />
<blockpin signalname="XLXN_43" name="CE" />
<blockpin signalname="XLXN_36" name="R" />
<blockpin signalname="XLXN_36" name="S" />
<blockpin signalname="XLXN_10" name="Q0" />
<blockpin signalname="XLXN_9" name="Q1" />
</block>
<block symbolname="iddr2" name="XLXI_203">
<blockpin signalname="LVDS_Channel3" name="D" />
<blockpin signalname="CMOS_CLK" name="C0" />
<blockpin signalname="CMOS_CLK_INV" name="C1" />
<blockpin signalname="XLXN_43" name="CE" />
<blockpin signalname="XLXN_38" name="R" />
<blockpin signalname="XLXN_38" name="S" />
<blockpin signalname="XLXN_12" name="Q0" />
<blockpin signalname="XLXN_11" name="Q1" />
</block>
<block symbolname="iddr2" name="XLXI_204">
<blockpin signalname="XLXN_49" name="D" />
<blockpin signalname="CMOS_CLK" name="C0" />
<blockpin signalname="CMOS_CLK_INV" name="C1" />
<blockpin signalname="XLXN_43" name="CE" />
<blockpin signalname="XLXN_40" name="R" />
<blockpin signalname="XLXN_40" name="S" />
<blockpin signalname="XLXN_14" name="Q0" />
<blockpin signalname="XLXN_13" name="Q1" />
</block>
<block symbolname="gnd" name="XLXI_205">
<blockpin signalname="XLXN_32" name="G" />
</block>
<block symbolname="gnd" name="XLXI_206">
<blockpin signalname="XLXN_34" name="G" />
</block>
<block symbolname="gnd" name="XLXI_207">
<blockpin signalname="XLXN_36" name="G" />
</block>
<block symbolname="gnd" name="XLXI_208">
<blockpin signalname="XLXN_38" name="G" />
</block>
<block symbolname="gnd" name="XLXI_209">
<blockpin signalname="XLXN_40" name="G" />
</block>
<block symbolname="vcc" name="XLXI_210">
<blockpin signalname="XLXN_43" name="P" />
</block>
<block symbolname="iodelay2" name="XLXI_213">
<attr value="FIXED" name="IDELAY_TYPE">
<trait editname="all:1 sch:0" />
<trait edittrait="all:1 sch:0" />
<trait verilog="all:0 dp:1nosynth wsynop:1 wsynth:1" />
<trait vhdl="all:0 gm:1nosynth wa:1 wd:1" />
<trait valuetype="StringValList DEFAULT DIFF_PHASE_DETECTOR FIXED VARIABLE_FROM_HALF_MAX VARIABLE_FROM_ZERO" />
</attr>
<attr value="IDATAIN" name="DELAY_SRC">
<trait editname="all:1 sch:0" />
<trait edittrait="all:1 sch:0" />
<trait verilog="all:0 dp:1nosynth wsynop:1 wsynth:1" />
<trait vhdl="all:0 gm:1nosynth wa:1 wd:1" />
<trait valuetype="StringValList IO IDATAIN ODATAIN" />
</attr>
<attr value="10" name="IDELAY_VALUE">
<trait editname="all:1 sch:0" />
<trait edittrait="all:1 sch:0" />
<trait verilog="all:0 dp:1nosynth wsynop:1 wsynth:1" />
<trait vhdl="all:0 gm:1nosynth wa:1 wd:1" />
<trait valuetype="Integer 0 255" />
</attr>
<attr value="DDR" name="DATA_RATE">
<trait editname="all:1 sch:0" />
<trait edittrait="all:1 sch:0" />
<trait verilog="all:0 dp:1nosynth wsynop:1 wsynth:1" />
<trait vhdl="all:0 gm:1nosynth wa:1 wd:1" />
<trait valuetype="StringValList SDR DDR" />
</attr>
<blockpin name="CAL" />
<blockpin name="CE" />
<blockpin name="CLK" />
<blockpin signalname="LVDS_Channel0" name="IDATAIN" />
<blockpin name="INC" />
<blockpin name="IOCLK0" />
<blockpin name="IOCLK1" />
<blockpin name="ODATAIN" />
<blockpin name="RST" />
<blockpin name="T" />
<blockpin name="BUSY" />
<blockpin signalname="XLXN_47" name="DATAOUT" />
<blockpin name="DATAOUT2" />
<blockpin name="DOUT" />
<blockpin name="TOUT" />
</block>
<block symbolname="iodelay2" name="XLXI_214">
<attr value="FIXED" name="IDELAY_TYPE">
<trait editname="all:1 sch:0" />
<trait edittrait="all:1 sch:0" />
<trait verilog="all:0 dp:1nosynth wsynop:1 wsynth:1" />
<trait vhdl="all:0 gm:1nosynth wa:1 wd:1" />
<trait valuetype="StringValList DEFAULT DIFF_PHASE_DETECTOR FIXED VARIABLE_FROM_HALF_MAX VARIABLE_FROM_ZERO" />
</attr>
<attr value="IDATAIN" name="DELAY_SRC">
<trait editname="all:1 sch:0" />
<trait edittrait="all:1 sch:0" />
<trait verilog="all:0 dp:1nosynth wsynop:1 wsynth:1" />
<trait vhdl="all:0 gm:1nosynth wa:1 wd:1" />
<trait valuetype="StringValList IO IDATAIN ODATAIN" />
</attr>
<attr value="10" name="IDELAY_VALUE">
<trait editname="all:1 sch:0" />
<trait edittrait="all:1 sch:0" />
<trait verilog="all:0 dp:1nosynth wsynop:1 wsynth:1" />
<trait vhdl="all:0 gm:1nosynth wa:1 wd:1" />
<trait valuetype="Integer 0 255" />
</attr>
<attr value="DDR" name="DATA_RATE">
<trait editname="all:1 sch:0" />
<trait edittrait="all:1 sch:0" />
<trait verilog="all:0 dp:1nosynth wsynop:1 wsynth:1" />
<trait vhdl="all:0 gm:1nosynth wa:1 wd:1" />
<trait valuetype="StringValList SDR DDR" />
</attr>
<blockpin name="CAL" />
<blockpin name="CE" />
<blockpin name="CLK" />
<blockpin signalname="LVDS_Sync" name="IDATAIN" />
<blockpin name="INC" />
<blockpin name="IOCLK0" />
<blockpin name="IOCLK1" />
<blockpin name="ODATAIN" />
<blockpin name="RST" />
<blockpin name="T" />
<blockpin name="BUSY" />
<blockpin signalname="XLXN_49" name="DATAOUT" />
<blockpin name="DATAOUT2" />
<blockpin name="DOUT" />
<blockpin name="TOUT" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="2176" y="400" name="XLXI_180" orien="R0" />
<instance x="2176" y="656" name="XLXI_181" orien="R0" />
<instance x="2176" y="912" name="XLXI_182" orien="R0" />
<instance x="2176" y="1424" name="XLXI_184" orien="R0" />
<instance x="2176" y="1936" name="XLXI_186" orien="R0" />
<instance x="2176" y="2192" name="XLXI_187" orien="R0" />
<instance x="2176" y="2448" name="XLXI_188" orien="R0" />
<instance x="2176" y="2704" name="XLXI_189" orien="R0" />
<instance x="2176" y="1680" name="XLXI_185" orien="R0" />
<instance x="2176" y="1168" name="XLXI_183" orien="R0" />
<instance x="1280" y="432" name="XLXI_200" orien="R0" />
<instance x="1280" y="944" name="XLXI_201" orien="R0" />
<instance x="1296" y="1968" name="XLXI_203" orien="R0" />
<instance x="1296" y="2480" name="XLXI_204" orien="R0" />
<branch name="XLXN_5">
<wire x2="1888" y1="240" y2="240" x1="1600" />
<wire x2="1888" y1="144" y2="240" x1="1888" />
<wire x2="2176" y1="144" y2="144" x1="1888" />
</branch>
<branch name="XLXN_6">
<wire x2="2176" y1="400" y2="400" x1="1600" />
</branch>
<branch name="XLXN_7">
<wire x2="1888" y1="752" y2="752" x1="1600" />
<wire x2="1888" y1="656" y2="752" x1="1888" />
<wire x2="2176" y1="656" y2="656" x1="1888" />
</branch>
<branch name="XLXN_8">
<wire x2="2176" y1="912" y2="912" x1="1600" />
</branch>
<branch name="XLXN_9">
<wire x2="2176" y1="1424" y2="1424" x1="1616" />
</branch>
<branch name="XLXN_10">
<wire x2="1760" y1="1264" y2="1264" x1="1616" />
<wire x2="1760" y1="1168" y2="1264" x1="1760" />
<wire x2="2176" y1="1168" y2="1168" x1="1760" />
</branch>
<instance x="1296" y="1456" name="XLXI_202" orien="R0" />
<branch name="XLXN_11">
<wire x2="2176" y1="1936" y2="1936" x1="1616" />
</branch>
<branch name="XLXN_12">
<wire x2="1888" y1="1776" y2="1776" x1="1616" />
<wire x2="1888" y1="1680" y2="1776" x1="1888" />
<wire x2="2176" y1="1680" y2="1680" x1="1888" />
</branch>
<branch name="XLXN_13">
<wire x2="2176" y1="2448" y2="2448" x1="1616" />
</branch>
<branch name="XLXN_14">
<wire x2="1888" y1="2288" y2="2288" x1="1616" />
<wire x2="1888" y1="2192" y2="2288" x1="1888" />
<wire x2="2176" y1="2192" y2="2192" x1="1888" />
</branch>
<branch name="CMOS_CLK">
<attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1968" y="272" type="branch" />
<wire x2="2048" y1="272" y2="272" x1="1968" />
<wire x2="2048" y1="272" y2="528" x1="2048" />
<wire x2="2048" y1="528" y2="784" x1="2048" />
<wire x2="2048" y1="784" y2="1040" x1="2048" />
<wire x2="2048" y1="1040" y2="1296" x1="2048" />
<wire x2="2048" y1="1296" y2="1552" x1="2048" />
<wire x2="2048" y1="1552" y2="1808" x1="2048" />
<wire x2="2048" y1="1808" y2="2064" x1="2048" />
<wire x2="2048" y1="2064" y2="2320" x1="2048" />
<wire x2="2048" y1="2320" y2="2576" x1="2048" />
<wire x2="2176" y1="2576" y2="2576" x1="2048" />
<wire x2="2176" y1="2320" y2="2320" x1="2048" />
<wire x2="2176" y1="2064" y2="2064" x1="2048" />
<wire x2="2176" y1="1808" y2="1808" x1="2048" />
<wire x2="2176" y1="1552" y2="1552" x1="2048" />
<wire x2="2176" y1="1296" y2="1296" x1="2048" />
<wire x2="2176" y1="1040" y2="1040" x1="2048" />
<wire x2="2176" y1="784" y2="784" x1="2048" />
<wire x2="2176" y1="528" y2="528" x1="2048" />
<wire x2="2176" y1="272" y2="272" x1="2048" />
</branch>
<branch name="LVDS_Channel1">
<wire x2="1264" y1="688" y2="688" x1="1072" />
<wire x2="1280" y1="688" y2="688" x1="1264" />
</branch>
<branch name="LVDS_Channel2">
<wire x2="1296" y1="1200" y2="1200" x1="928" />
</branch>
<branch name="LVDS_Channel3">
<wire x2="1296" y1="1712" y2="1712" x1="944" />
</branch>
<branch name="CMOS_CLK">
<wire x2="1104" y1="240" y2="240" x1="1056" />
<wire x2="1104" y1="240" y2="752" x1="1104" />
<wire x2="1280" y1="752" y2="752" x1="1104" />
<wire x2="1104" y1="752" y2="1264" x1="1104" />
<wire x2="1296" y1="1264" y2="1264" x1="1104" />
<wire x2="1104" y1="1264" y2="1776" x1="1104" />
<wire x2="1296" y1="1776" y2="1776" x1="1104" />
<wire x2="1104" y1="1776" y2="2288" x1="1104" />
<wire x2="1296" y1="2288" y2="2288" x1="1104" />
<wire x2="1280" y1="240" y2="240" x1="1104" />
</branch>
<branch name="CMOS_CLK_INV">
<wire x2="1152" y1="304" y2="304" x1="1056" />
<wire x2="1152" y1="304" y2="816" x1="1152" />
<wire x2="1280" y1="816" y2="816" x1="1152" />
<wire x2="1152" y1="816" y2="1328" x1="1152" />
<wire x2="1296" y1="1328" y2="1328" x1="1152" />
<wire x2="1152" y1="1328" y2="1840" x1="1152" />
<wire x2="1296" y1="1840" y2="1840" x1="1152" />
<wire x2="1152" y1="1840" y2="2352" x1="1152" />
<wire x2="1296" y1="2352" y2="2352" x1="1152" />
<wire x2="1280" y1="304" y2="304" x1="1152" />
</branch>
<iomarker fontsize="28" x="928" y="1200" name="LVDS_Channel2" orien="R180" />
<iomarker fontsize="28" x="944" y="1712" name="LVDS_Channel3" orien="R180" />
<iomarker fontsize="28" x="1056" y="304" name="CMOS_CLK_INV" orien="R180" />
<iomarker fontsize="28" x="1056" y="240" name="CMOS_CLK" orien="R180" />
<instance x="1152" y="656" name="XLXI_205" orien="R0" />
<instance x="1152" y="1184" name="XLXI_206" orien="R0" />
<instance x="1152" y="1696" name="XLXI_207" orien="R0" />
<instance x="1152" y="2688" name="XLXI_209" orien="R0" />
<instance x="1152" y="2208" name="XLXI_208" orien="R0" />
<branch name="XLXN_32">
<wire x2="1280" y1="432" y2="432" x1="1216" />
<wire x2="1216" y1="432" y2="496" x1="1216" />
<wire x2="1280" y1="496" y2="496" x1="1216" />
<wire x2="1216" y1="496" y2="528" x1="1216" />
</branch>
<branch name="XLXN_34">
<wire x2="1280" y1="944" y2="944" x1="1216" />
<wire x2="1216" y1="944" y2="1008" x1="1216" />
<wire x2="1280" y1="1008" y2="1008" x1="1216" />
<wire x2="1216" y1="1008" y2="1056" x1="1216" />
</branch>
<branch name="XLXN_36">
<wire x2="1296" y1="1456" y2="1456" x1="1216" />
<wire x2="1216" y1="1456" y2="1520" x1="1216" />
<wire x2="1296" y1="1520" y2="1520" x1="1216" />
<wire x2="1216" y1="1520" y2="1568" x1="1216" />
</branch>
<branch name="XLXN_38">
<wire x2="1296" y1="1968" y2="1968" x1="1216" />
<wire x2="1216" y1="1968" y2="2032" x1="1216" />
<wire x2="1296" y1="2032" y2="2032" x1="1216" />
<wire x2="1216" y1="2032" y2="2080" x1="1216" />
</branch>
<branch name="XLXN_40">
<wire x2="1296" y1="2480" y2="2480" x1="1216" />
<wire x2="1216" y1="2480" y2="2544" x1="1216" />
<wire x2="1296" y1="2544" y2="2544" x1="1216" />
<wire x2="1216" y1="2544" y2="2560" x1="1216" />
</branch>
<instance x="1184" y="128" name="XLXI_210" orien="R0" />
<branch name="XLXN_43">
<wire x2="1248" y1="128" y2="368" x1="1248" />
<wire x2="1280" y1="368" y2="368" x1="1248" />
<wire x2="1248" y1="368" y2="880" x1="1248" />
<wire x2="1280" y1="880" y2="880" x1="1248" />
<wire x2="1248" y1="880" y2="1392" x1="1248" />
<wire x2="1296" y1="1392" y2="1392" x1="1248" />
<wire x2="1248" y1="1392" y2="1904" x1="1248" />
<wire x2="1296" y1="1904" y2="1904" x1="1248" />
<wire x2="1248" y1="1904" y2="2416" x1="1248" />
<wire x2="1296" y1="2416" y2="2416" x1="1248" />
</branch>
<branch name="Channel_0_P">
<wire x2="2592" y1="144" y2="144" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="144" name="Channel_0_P" orien="R0" />
<branch name="Channel_0_N">
<wire x2="2592" y1="400" y2="400" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="400" name="Channel_0_N" orien="R0" />
<branch name="Channel_1_P">
<wire x2="2592" y1="656" y2="656" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="656" name="Channel_1_P" orien="R0" />
<branch name="Channel_1_N">
<wire x2="2592" y1="912" y2="912" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="912" name="Channel_1_N" orien="R0" />
<branch name="Channel_2_P">
<wire x2="2592" y1="1168" y2="1168" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="1168" name="Channel_2_P" orien="R0" />
<branch name="Channel_2_N">
<wire x2="2592" y1="1424" y2="1424" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="1424" name="Channel_2_N" orien="R0" />
<branch name="Channel_3_P">
<wire x2="2592" y1="1680" y2="1680" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="1680" name="Channel_3_P" orien="R0" />
<branch name="Channel_3_N">
<wire x2="2592" y1="1936" y2="1936" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="1936" name="Channel_3_N" orien="R0" />
<branch name="Sync_P">
<wire x2="2592" y1="2192" y2="2192" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="2192" name="Sync_P" orien="R0" />
<branch name="Sync_N">
<wire x2="2592" y1="2448" y2="2448" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="2448" name="Sync_N" orien="R0" />
<iomarker fontsize="28" x="1072" y="688" name="LVDS_Channel1" orien="R180" />
<instance x="320" y="768" name="XLXI_213" orien="R0">
<attrtext style="fontsize:28;fontname:Arial;displayformat:NAMEEQUALSVALUE" attrname="IDELAY_TYPE" x="192" y="-380" type="instance" />
<attrtext style="fontsize:28;fontname:Arial;displayformat:NAMEEQUALSVALUE" attrname="DELAY_SRC" x="223" y="-380" type="instance" />
<attrtext style="fontsize:28;fontname:Arial;displayformat:NAMEEQUALSVALUE" attrname="IDELAY_VALUE" x="241" y="-380" type="instance" />
<attrtext style="fontsize:28;fontname:Arial;displayformat:NAMEEQUALSVALUE" attrname="DATA_RATE" x="241" y="-380" type="instance" />
</instance>
<branch name="XLXN_47">
<wire x2="768" y1="304" y2="304" x1="704" />
<wire x2="768" y1="176" y2="304" x1="768" />
<wire x2="1280" y1="176" y2="176" x1="768" />
</branch>
<branch name="LVDS_Channel0">
<wire x2="320" y1="352" y2="352" x1="288" />
</branch>
<iomarker fontsize="28" x="288" y="352" name="LVDS_Channel0" orien="R180" />
<instance x="416" y="2640" name="XLXI_214" orien="R0">
<attrtext style="fontsize:28;fontname:Arial;displayformat:NAMEEQUALSVALUE" attrname="IDELAY_TYPE" x="192" y="-380" type="instance" />
<attrtext style="fontsize:28;fontname:Arial;displayformat:NAMEEQUALSVALUE" attrname="DELAY_SRC" x="223" y="-380" type="instance" />
<attrtext style="fontsize:28;fontname:Arial;displayformat:NAMEEQUALSVALUE" attrname="IDELAY_VALUE" x="241" y="-380" type="instance" />
<attrtext style="fontsize:28;fontname:Arial;displayformat:NAMEEQUALSVALUE" attrname="DATA_RATE" x="241" y="-380" type="instance" />
</instance>
<branch name="XLXN_49">
<wire x2="1040" y1="2176" y2="2176" x1="800" />
<wire x2="1040" y1="2176" y2="2224" x1="1040" />
<wire x2="1296" y1="2224" y2="2224" x1="1040" />
</branch>
<branch name="LVDS_Sync">
<wire x2="416" y1="2224" y2="2224" x1="384" />
</branch>
<iomarker fontsize="28" x="384" y="2224" name="LVDS_Sync" orien="R180" />
</sheet>
</drawing>

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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="LVDS_IDDR">
<symboltype>BLOCK</symboltype>
<timestamp>2017-9-27T11:46:54</timestamp>
<pin polarity="Input" x="0" y="-608" name="LVDS_Channel0" />
<pin polarity="Output" x="544" y="-512" name="Channel_1_P" />
<pin polarity="Output" x="544" y="-448" name="Channel_1_N" />
<pin polarity="Output" x="544" y="-640" name="Channel_0_P" />
<pin polarity="Output" x="544" y="-576" name="Channel_0_N" />
<pin polarity="Output" x="544" y="-384" name="Channel_2_P" />
<pin polarity="Output" x="544" y="-320" name="Channel_2_N" />
<pin polarity="Output" x="544" y="-256" name="Channel_3_P" />
<pin polarity="Output" x="544" y="-192" name="Channel_3_N" />
<pin polarity="Output" x="544" y="-128" name="Sync_P" />
<pin polarity="Output" x="544" y="-64" name="Sync_N" />
<pin polarity="Input" x="0" y="-480" name="LVDS_Channel1" />
<pin polarity="Input" x="0" y="-96" name="LVDS_Sync" />
<pin polarity="Input" x="0" y="-224" name="LVDS_Channel3" />
<pin polarity="Input" x="0" y="-352" name="LVDS_Channel2" />
<pin polarity="Input" x="0" y="-688" name="CMOS_CLK_INV" />
<pin polarity="Input" x="0" y="-736" name="CMOS_CLK" />
<graph>
<rect width="416" x="64" y="-756" height="756" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-608" type="pin LVDS_Channel0" />
<line x2="0" y1="-608" y2="-608" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-512" type="pin Channel_1_P" />
<line x2="544" y1="-512" y2="-512" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-448" type="pin Channel_1_N" />
<line x2="544" y1="-448" y2="-448" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-640" type="pin Channel_0_P" />
<line x2="544" y1="-640" y2="-640" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-576" type="pin Channel_0_N" />
<line x2="544" y1="-576" y2="-576" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-384" type="pin Channel_2_P" />
<line x2="544" y1="-384" y2="-384" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-320" type="pin Channel_2_N" />
<line x2="544" y1="-320" y2="-320" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-256" type="pin Channel_3_P" />
<line x2="544" y1="-256" y2="-256" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-192" type="pin Channel_3_N" />
<line x2="544" y1="-192" y2="-192" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-128" type="pin Sync_P" />
<line x2="544" y1="-128" y2="-128" x1="480" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="472" y="-64" type="pin Sync_N" />
<line x2="544" y1="-64" y2="-64" x1="480" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin LVDS_Channel1" />
<line x2="0" y1="-480" y2="-480" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin LVDS_Sync" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin LVDS_Channel3" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin LVDS_Channel2" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="268" y="-764" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-688" type="pin CMOS_CLK_INV" />
<line x2="0" y1="-688" y2="-688" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-736" type="pin CMOS_CLK" />
<line x2="0" y1="-736" y2="-736" x1="64" />
</graph>
</symbol>

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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : sch2hdl
// / / Filename : LVDS_IDDR.vf
// /___/ /\ Timestamp : 11/03/2017 21:03:49
// \ \ / \
// \___\/\___\
//
//Command: sch2hdl -sympath D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/ipcore_dir -intstyle ise -family spartan6 -verilog D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/LVDS_IDDR.vf -w D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/LVDS_IDDR.sch
//Design Name: LVDS_IDDR
//Device: spartan6
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module LVDS_IDDR(CMOS_CLK,
CMOS_CLK_INV,
LVDS_Channel0,
LVDS_Channel1,
LVDS_Channel2,
LVDS_Channel3,
LVDS_Sync,
Channel_0_N,
Channel_0_P,
Channel_1_N,
Channel_1_P,
Channel_2_N,
Channel_2_P,
Channel_3_N,
Channel_3_P,
Sync_N,
Sync_P);
input CMOS_CLK;
input CMOS_CLK_INV;
input LVDS_Channel0;
input LVDS_Channel1;
input LVDS_Channel2;
input LVDS_Channel3;
input LVDS_Sync;
output Channel_0_N;
output Channel_0_P;
output Channel_1_N;
output Channel_1_P;
output Channel_2_N;
output Channel_2_P;
output Channel_3_N;
output Channel_3_P;
output Sync_N;
output Sync_P;
wire XLXN_5;
wire XLXN_6;
wire XLXN_7;
wire XLXN_8;
wire XLXN_9;
wire XLXN_10;
wire XLXN_11;
wire XLXN_12;
wire XLXN_13;
wire XLXN_14;
wire XLXN_32;
wire XLXN_34;
wire XLXN_36;
wire XLXN_38;
wire XLXN_40;
wire XLXN_43;
wire XLXN_47;
wire XLXN_49;
FD #( .INIT(1'b0) ) XLXI_180 (.C(CMOS_CLK),
.D(XLXN_5),
.Q(Channel_0_P));
FD #( .INIT(1'b0) ) XLXI_181 (.C(CMOS_CLK),
.D(XLXN_6),
.Q(Channel_0_N));
FD #( .INIT(1'b0) ) XLXI_182 (.C(CMOS_CLK),
.D(XLXN_7),
.Q(Channel_1_P));
FD #( .INIT(1'b0) ) XLXI_183 (.C(CMOS_CLK),
.D(XLXN_8),
.Q(Channel_1_N));
FD #( .INIT(1'b0) ) XLXI_184 (.C(CMOS_CLK),
.D(XLXN_10),
.Q(Channel_2_P));
FD #( .INIT(1'b0) ) XLXI_185 (.C(CMOS_CLK),
.D(XLXN_9),
.Q(Channel_2_N));
FD #( .INIT(1'b0) ) XLXI_186 (.C(CMOS_CLK),
.D(XLXN_12),
.Q(Channel_3_P));
FD #( .INIT(1'b0) ) XLXI_187 (.C(CMOS_CLK),
.D(XLXN_11),
.Q(Channel_3_N));
FD #( .INIT(1'b0) ) XLXI_188 (.C(CMOS_CLK),
.D(XLXN_14),
.Q(Sync_P));
FD #( .INIT(1'b0) ) XLXI_189 (.C(CMOS_CLK),
.D(XLXN_13),
.Q(Sync_N));
IDDR2 #( .INIT_Q0(1'b0), .INIT_Q1(1'b0), .SRTYPE("SYNC"),
.DDR_ALIGNMENT("NONE") ) XLXI_200 (.CE(XLXN_43),
.C0(CMOS_CLK),
.C1(CMOS_CLK_INV),
.D(XLXN_47),
.R(XLXN_32),
.S(XLXN_32),
.Q0(XLXN_5),
.Q1(XLXN_6));
IDDR2 #( .INIT_Q0(1'b0), .INIT_Q1(1'b0), .SRTYPE("SYNC"),
.DDR_ALIGNMENT("NONE") ) XLXI_201 (.CE(XLXN_43),
.C0(CMOS_CLK),
.C1(CMOS_CLK_INV),
.D(LVDS_Channel1),
.R(XLXN_34),
.S(XLXN_34),
.Q0(XLXN_7),
.Q1(XLXN_8));
IDDR2 #( .INIT_Q0(1'b0), .INIT_Q1(1'b0), .SRTYPE("SYNC"),
.DDR_ALIGNMENT("NONE") ) XLXI_202 (.CE(XLXN_43),
.C0(CMOS_CLK),
.C1(CMOS_CLK_INV),
.D(LVDS_Channel2),
.R(XLXN_36),
.S(XLXN_36),
.Q0(XLXN_10),
.Q1(XLXN_9));
IDDR2 #( .INIT_Q0(1'b0), .INIT_Q1(1'b0), .SRTYPE("SYNC"),
.DDR_ALIGNMENT("NONE") ) XLXI_203 (.CE(XLXN_43),
.C0(CMOS_CLK),
.C1(CMOS_CLK_INV),
.D(LVDS_Channel3),
.R(XLXN_38),
.S(XLXN_38),
.Q0(XLXN_12),
.Q1(XLXN_11));
IDDR2 #( .INIT_Q0(1'b0), .INIT_Q1(1'b0), .SRTYPE("SYNC"),
.DDR_ALIGNMENT("NONE") ) XLXI_204 (.CE(XLXN_43),
.C0(CMOS_CLK),
.C1(CMOS_CLK_INV),
.D(XLXN_49),
.R(XLXN_40),
.S(XLXN_40),
.Q0(XLXN_14),
.Q1(XLXN_13));
GND XLXI_205 (.G(XLXN_32));
GND XLXI_206 (.G(XLXN_34));
GND XLXI_207 (.G(XLXN_36));
GND XLXI_208 (.G(XLXN_38));
GND XLXI_209 (.G(XLXN_40));
VCC XLXI_210 (.P(XLXN_43));
IODELAY2 #( .IDELAY_TYPE("FIXED"), .DELAY_SRC("IDATAIN"), .IDELAY_VALUE(10),
.DATA_RATE("DDR"), .COUNTER_WRAPAROUND("WRAPAROUND"),
.IDELAY2_VALUE(0), .IDELAY_MODE("NORMAL"), .ODELAY_VALUE(0),
.SERDES_MODE("NONE"), .SIM_TAPDELAY_VALUE(75) ) XLXI_213 (.CAL(),
.CE(),
.CLK(),
.IDATAIN(LVDS_Channel0),
.INC(),
.IOCLK0(),
.IOCLK1(),
.ODATAIN(),
.RST(),
.T(),
.BUSY(),
.DATAOUT(XLXN_47),
.DATAOUT2(),
.DOUT(),
.TOUT());
IODELAY2 #( .IDELAY_TYPE("FIXED"), .DELAY_SRC("IDATAIN"), .IDELAY_VALUE(10),
.DATA_RATE("DDR"), .COUNTER_WRAPAROUND("WRAPAROUND"),
.IDELAY2_VALUE(0), .IDELAY_MODE("NORMAL"), .ODELAY_VALUE(0),
.SERDES_MODE("NONE"), .SIM_TAPDELAY_VALUE(75) ) XLXI_214 (.CAL(),
.CE(),
.CLK(),
.IDATAIN(LVDS_Sync),
.INC(),
.IOCLK0(),
.IOCLK1(),
.ODATAIN(),
.RST(),
.T(),
.BUSY(),
.DATAOUT(XLXN_49),
.DATAOUT2(),
.DOUT(),
.TOUT());
endmodule

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#ChipScope Core Inserter Project File Version 3.0
#Tue Sep 12 22:12:29 CST 2017
Project.device.designInputFile=D\:\\03_FPGA_Project\\01_UAV_CMOS\\02_FPGA\\UAV_CMOS\\UAV_CMOS\\main_cs.ngc
Project.device.designOutputFile=D\:\\03_FPGA_Project\\01_UAV_CMOS\\02_FPGA\\UAV_CMOS\\UAV_CMOS\\main_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=D\:\\03_FPGA_Project\\01_UAV_CMOS\\02_FPGA\\UAV_CMOS\\UAV_CMOS\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=7
Project.filter<0>=*SPI_state*
Project.filter<1>=*sclk_buf*
Project.filter<2>=*data_read*
Project.filter<3>=*shift*
Project.filter<4>=
Project.filter<5>=*MOSI*
Project.filter<6>=*SPI_bus_counter*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=SPI_CLK_10M
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=XLXN_16
Project.unit<0>.dataChannel<10>=XLXI_1/SPI_bus_counter<4>
Project.unit<0>.dataChannel<1>=XLXN_17<7>
Project.unit<0>.dataChannel<2>=XLXI_1/SS_N
Project.unit<0>.dataChannel<3>=XLXI_1/SCLK
Project.unit<0>.dataChannel<4>=XLXI_1/MOSI
Project.unit<0>.dataChannel<5>=SPI_MISO_IBUF
Project.unit<0>.dataChannel<6>=XLXI_1/SPI_bus_counter<0>
Project.unit<0>.dataChannel<7>=XLXI_1/SPI_bus_counter<1>
Project.unit<0>.dataChannel<8>=XLXI_1/SPI_bus_counter<2>
Project.unit<0>.dataChannel<9>=XLXI_1/SPI_bus_counter<3>
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=50
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=XLXN_16
Project.unit<0>.triggerChannel<0><1>=XLXN_17<7>
Project.unit<0>.triggerChannel<0><2>=XLXI_1/SS_N
Project.unit<0>.triggerChannel<0><3>=XLXI_1/SCLK
Project.unit<0>.triggerChannel<0><4>=XLXI_1/MOSI
Project.unit<0>.triggerChannel<0><5>=SPI_MISO_IBUF
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810
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI.cpj Normal file
View File

@ -0,0 +1,810 @@
#ChipScope Pro Analyzer Project File, Version 3.0
#Tue Sep 12 22:58:58 CST 2017
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unit.0.0.port.-1.s.34.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.34.name=DataPort[34]
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unit.0.0.port.-1.s.34.visible=0
unit.0.0.port.-1.s.35.alias=data_read8
unit.0.0.port.-1.s.35.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.35.name=DataPort[35]
unit.0.0.port.-1.s.35.orderindex=-1
unit.0.0.port.-1.s.35.visible=0
unit.0.0.port.-1.s.36.alias=data_read9
unit.0.0.port.-1.s.36.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.36.name=DataPort[36]
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unit.0.0.port.-1.s.36.visible=0
unit.0.0.port.-1.s.37.alias=data_read10
unit.0.0.port.-1.s.37.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.37.name=DataPort[37]
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unit.0.0.port.-1.s.37.visible=0
unit.0.0.port.-1.s.38.alias=data_read11
unit.0.0.port.-1.s.38.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.38.name=DataPort[38]
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unit.0.0.port.-1.s.38.visible=0
unit.0.0.port.-1.s.39.alias=data_read12
unit.0.0.port.-1.s.39.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.39.name=DataPort[39]
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unit.0.0.port.-1.s.39.visible=0
unit.0.0.port.-1.s.4.alias=MOSI
unit.0.0.port.-1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.4.visible=1
unit.0.0.port.-1.s.40.alias=data_read13
unit.0.0.port.-1.s.40.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.40.name=DataPort[40]
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unit.0.0.port.-1.s.40.visible=0
unit.0.0.port.-1.s.41.alias=data_read14
unit.0.0.port.-1.s.41.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.41.name=DataPort[41]
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unit.0.0.port.-1.s.41.visible=0
unit.0.0.port.-1.s.42.alias=data_read15
unit.0.0.port.-1.s.42.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.42.visible=0
unit.0.0.port.-1.s.43.alias=sclk_buf
unit.0.0.port.-1.s.43.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.43.visible=1
unit.0.0.port.-1.s.44.alias=SPI_state0
unit.0.0.port.-1.s.44.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.44.visible=0
unit.0.0.port.-1.s.45.alias=SPI_state1
unit.0.0.port.-1.s.45.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.45.visible=0
unit.0.0.port.-1.s.46.alias=SPI_state2
unit.0.0.port.-1.s.46.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.46.visible=0
unit.0.0.port.-1.s.47.alias=SPI_state3
unit.0.0.port.-1.s.47.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.47.visible=0
unit.0.0.port.-1.s.48.alias=SPI_state4
unit.0.0.port.-1.s.48.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.48.visible=0
unit.0.0.port.-1.s.49.alias=SPI_state5
unit.0.0.port.-1.s.49.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.49.name=DataPort[49]
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unit.0.0.port.-1.s.49.visible=0
unit.0.0.port.-1.s.5.alias=MISO
unit.0.0.port.-1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.5.visible=1
unit.0.0.port.-1.s.6.alias=SPI_BUS_COUNTER_0
unit.0.0.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.6.name=DataPort[6]
unit.0.0.port.-1.s.6.orderindex=-1
unit.0.0.port.-1.s.6.visible=0
unit.0.0.port.-1.s.7.alias=SPI_BUS_COUNTER_1
unit.0.0.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.7.visible=0
unit.0.0.port.-1.s.8.alias=SPI_BUS_COUNTER_2
unit.0.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.8.orderindex=-1
unit.0.0.port.-1.s.8.visible=0
unit.0.0.port.-1.s.9.alias=SPI_BUS_COUNTER_3
unit.0.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.-1.s.9.visible=0
unit.0.0.port.0.b.0.alias=
unit.0.0.port.0.b.0.channellist=0 1 2 3 4 5
unit.0.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.b.0.name=TriggerPort0
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unit.0.0.port.0.b.0.radix=Hex
unit.0.0.port.0.b.0.signedOffset=0.0
unit.0.0.port.0.b.0.signedPrecision=0
unit.0.0.port.0.b.0.signedScaleFactor=1.0
unit.0.0.port.0.b.0.unsignedOffset=0.0
unit.0.0.port.0.b.0.unsignedPrecision=0
unit.0.0.port.0.b.0.unsignedScaleFactor=1.0
unit.0.0.port.0.b.0.visible=1
unit.0.0.port.0.buscount=1
unit.0.0.port.0.channelcount=6
unit.0.0.port.0.s.0.alias=Reset
unit.0.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.0.name=TriggerPort0[0]
unit.0.0.port.0.s.0.orderindex=-1
unit.0.0.port.0.s.0.visible=1
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unit.0.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.1.name=TriggerPort0[1]
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unit.0.0.port.0.s.1.visible=1
unit.0.0.port.0.s.2.alias=SS_N
unit.0.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.2.name=TriggerPort0[2]
unit.0.0.port.0.s.2.orderindex=-1
unit.0.0.port.0.s.2.visible=1
unit.0.0.port.0.s.3.alias=SCLK
unit.0.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.3.name=TriggerPort0[3]
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unit.0.0.port.0.s.3.visible=1
unit.0.0.port.0.s.4.alias=MOSI
unit.0.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.4.name=TriggerPort0[4]
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unit.0.0.port.0.s.4.visible=1
unit.0.0.port.0.s.5.alias=MISO
unit.0.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.0.s.5.visible=1
unit.0.0.port.1.b.0.alias=
unit.0.0.port.1.b.0.channellist=0 1 2 3 4
unit.0.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.1.b.0.radix=Hex
unit.0.0.port.1.b.0.signedOffset=0.0
unit.0.0.port.1.b.0.signedPrecision=0
unit.0.0.port.1.b.0.signedScaleFactor=1.0
unit.0.0.port.1.b.0.unsignedOffset=0.0
unit.0.0.port.1.b.0.unsignedPrecision=0
unit.0.0.port.1.b.0.unsignedScaleFactor=1.0
unit.0.0.port.1.b.0.visible=1
unit.0.0.port.1.buscount=1
unit.0.0.port.1.channelcount=5
unit.0.0.port.1.s.0.alias=SPI_BUS_COUNTER_0
unit.0.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.1.s.0.name=TriggerPort1[0]
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unit.0.0.port.1.s.0.visible=1
unit.0.0.port.1.s.1.alias=SPI_BUS_COUNTER_1
unit.0.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.1.s.1.name=TriggerPort1[1]
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unit.0.0.port.1.s.1.visible=1
unit.0.0.port.1.s.2.alias=SPI_BUS_COUNTER_2
unit.0.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.1.s.2.name=TriggerPort1[2]
unit.0.0.port.1.s.2.orderindex=-1
unit.0.0.port.1.s.2.visible=1
unit.0.0.port.1.s.3.alias=SPI_BUS_COUNTER_3
unit.0.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.1.s.3.name=TriggerPort1[3]
unit.0.0.port.1.s.3.orderindex=-1
unit.0.0.port.1.s.3.visible=1
unit.0.0.port.1.s.4.alias=SPI_BUS_COUNTER_4
unit.0.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.1.s.4.name=TriggerPort1[4]
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unit.0.0.port.1.s.4.visible=1
unit.0.0.port.2.b.0.alias=
unit.0.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
unit.0.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.2.b.0.radix=Hex
unit.0.0.port.2.b.0.signedOffset=0.0
unit.0.0.port.2.b.0.signedPrecision=0
unit.0.0.port.2.b.0.signedScaleFactor=1.0
unit.0.0.port.2.b.0.unsignedOffset=0.0
unit.0.0.port.2.b.0.unsignedPrecision=0
unit.0.0.port.2.b.0.unsignedScaleFactor=1.0
unit.0.0.port.2.b.0.visible=1
unit.0.0.port.2.buscount=1
unit.0.0.port.2.channelcount=16
unit.0.0.port.2.s.0.alias=data_read_shift0
unit.0.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.2.s.0.visible=1
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unit.0.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.2.s.1.visible=1
unit.0.0.port.2.s.10.alias=data_read_shift10
unit.0.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.2.s.10.visible=1
unit.0.0.port.2.s.11.alias=data_read_shift11
unit.0.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.11.name=TriggerPort2[11]
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unit.0.0.port.2.s.11.visible=1
unit.0.0.port.2.s.12.alias=data_read_shift12
unit.0.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.12.name=TriggerPort2[12]
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unit.0.0.port.2.s.12.visible=1
unit.0.0.port.2.s.13.alias=data_read_shift13
unit.0.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.13.name=TriggerPort2[13]
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unit.0.0.port.2.s.13.visible=1
unit.0.0.port.2.s.14.alias=data_read_shift14
unit.0.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.14.name=TriggerPort2[14]
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unit.0.0.port.2.s.14.visible=1
unit.0.0.port.2.s.15.alias=data_read_shift15
unit.0.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.15.name=TriggerPort2[15]
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unit.0.0.port.2.s.15.visible=1
unit.0.0.port.2.s.2.alias=data_read_shift2
unit.0.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.2.name=TriggerPort2[2]
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unit.0.0.port.2.s.2.visible=1
unit.0.0.port.2.s.3.alias=data_read_shift3
unit.0.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.3.name=TriggerPort2[3]
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unit.0.0.port.2.s.3.visible=1
unit.0.0.port.2.s.4.alias=data_read_shift4
unit.0.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.2.s.4.visible=1
unit.0.0.port.2.s.5.alias=data_read_shift5
unit.0.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.5.name=TriggerPort2[5]
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unit.0.0.port.2.s.5.visible=1
unit.0.0.port.2.s.6.alias=data_read_shift6
unit.0.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.6.name=TriggerPort2[6]
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unit.0.0.port.2.s.6.visible=1
unit.0.0.port.2.s.7.alias=data_read_shift7
unit.0.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.7.name=TriggerPort2[7]
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unit.0.0.port.2.s.7.visible=1
unit.0.0.port.2.s.8.alias=data_read_shift8
unit.0.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.8.name=TriggerPort2[8]
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unit.0.0.port.2.s.8.visible=1
unit.0.0.port.2.s.9.alias=data_read_shift9
unit.0.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.2.s.9.name=TriggerPort2[9]
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unit.0.0.port.2.s.9.visible=1
unit.0.0.port.3.b.0.alias=
unit.0.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
unit.0.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
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unit.0.0.port.3.b.0.radix=Hex
unit.0.0.port.3.b.0.signedOffset=0.0
unit.0.0.port.3.b.0.signedPrecision=0
unit.0.0.port.3.b.0.signedScaleFactor=1.0
unit.0.0.port.3.b.0.unsignedOffset=0.0
unit.0.0.port.3.b.0.unsignedPrecision=0
unit.0.0.port.3.b.0.unsignedScaleFactor=1.0
unit.0.0.port.3.b.0.visible=1
unit.0.0.port.3.buscount=1
unit.0.0.port.3.channelcount=16
unit.0.0.port.3.s.0.alias=data_read0
unit.0.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.0.name=TriggerPort3[0]
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unit.0.0.port.3.s.0.visible=1
unit.0.0.port.3.s.1.alias=data_read1
unit.0.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.1.name=TriggerPort3[1]
unit.0.0.port.3.s.1.orderindex=-1
unit.0.0.port.3.s.1.visible=1
unit.0.0.port.3.s.10.alias=data_read10
unit.0.0.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.10.name=TriggerPort3[10]
unit.0.0.port.3.s.10.orderindex=-1
unit.0.0.port.3.s.10.visible=1
unit.0.0.port.3.s.11.alias=data_read11
unit.0.0.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.11.name=TriggerPort3[11]
unit.0.0.port.3.s.11.orderindex=-1
unit.0.0.port.3.s.11.visible=1
unit.0.0.port.3.s.12.alias=data_read12
unit.0.0.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.12.name=TriggerPort3[12]
unit.0.0.port.3.s.12.orderindex=-1
unit.0.0.port.3.s.12.visible=1
unit.0.0.port.3.s.13.alias=data_read13
unit.0.0.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.13.name=TriggerPort3[13]
unit.0.0.port.3.s.13.orderindex=-1
unit.0.0.port.3.s.13.visible=1
unit.0.0.port.3.s.14.alias=data_read14
unit.0.0.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.14.name=TriggerPort3[14]
unit.0.0.port.3.s.14.orderindex=-1
unit.0.0.port.3.s.14.visible=1
unit.0.0.port.3.s.15.alias=data_read15
unit.0.0.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.15.name=TriggerPort3[15]
unit.0.0.port.3.s.15.orderindex=-1
unit.0.0.port.3.s.15.visible=1
unit.0.0.port.3.s.2.alias=data_read2
unit.0.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.2.name=TriggerPort3[2]
unit.0.0.port.3.s.2.orderindex=-1
unit.0.0.port.3.s.2.visible=1
unit.0.0.port.3.s.3.alias=data_read3
unit.0.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.3.name=TriggerPort3[3]
unit.0.0.port.3.s.3.orderindex=-1
unit.0.0.port.3.s.3.visible=1
unit.0.0.port.3.s.4.alias=data_read4
unit.0.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.4.name=TriggerPort3[4]
unit.0.0.port.3.s.4.orderindex=-1
unit.0.0.port.3.s.4.visible=1
unit.0.0.port.3.s.5.alias=data_read5
unit.0.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.5.name=TriggerPort3[5]
unit.0.0.port.3.s.5.orderindex=-1
unit.0.0.port.3.s.5.visible=1
unit.0.0.port.3.s.6.alias=data_read6
unit.0.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.6.name=TriggerPort3[6]
unit.0.0.port.3.s.6.orderindex=-1
unit.0.0.port.3.s.6.visible=1
unit.0.0.port.3.s.7.alias=data_read7
unit.0.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.7.name=TriggerPort3[7]
unit.0.0.port.3.s.7.orderindex=-1
unit.0.0.port.3.s.7.visible=1
unit.0.0.port.3.s.8.alias=data_read8
unit.0.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.8.name=TriggerPort3[8]
unit.0.0.port.3.s.8.orderindex=-1
unit.0.0.port.3.s.8.visible=1
unit.0.0.port.3.s.9.alias=data_read9
unit.0.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.3.s.9.name=TriggerPort3[9]
unit.0.0.port.3.s.9.orderindex=-1
unit.0.0.port.3.s.9.visible=1
unit.0.0.port.4.b.0.alias=
unit.0.0.port.4.b.0.channellist=0
unit.0.0.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.4.b.0.name=TriggerPort4
unit.0.0.port.4.b.0.orderindex=-1
unit.0.0.port.4.b.0.radix=Hex
unit.0.0.port.4.b.0.signedOffset=0.0
unit.0.0.port.4.b.0.signedPrecision=0
unit.0.0.port.4.b.0.signedScaleFactor=1.0
unit.0.0.port.4.b.0.unsignedOffset=0.0
unit.0.0.port.4.b.0.unsignedPrecision=0
unit.0.0.port.4.b.0.unsignedScaleFactor=1.0
unit.0.0.port.4.b.0.visible=1
unit.0.0.port.4.buscount=1
unit.0.0.port.4.channelcount=1
unit.0.0.port.4.s.0.alias=sclk_buf
unit.0.0.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.4.s.0.name=TriggerPort4[0]
unit.0.0.port.4.s.0.orderindex=-1
unit.0.0.port.4.s.0.visible=1
unit.0.0.port.5.b.0.alias=
unit.0.0.port.5.b.0.channellist=0 1 2 3 4 5
unit.0.0.port.5.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.5.b.0.name=TriggerPort5
unit.0.0.port.5.b.0.orderindex=-1
unit.0.0.port.5.b.0.radix=Hex
unit.0.0.port.5.b.0.signedOffset=0.0
unit.0.0.port.5.b.0.signedPrecision=0
unit.0.0.port.5.b.0.signedScaleFactor=1.0
unit.0.0.port.5.b.0.unsignedOffset=0.0
unit.0.0.port.5.b.0.unsignedPrecision=0
unit.0.0.port.5.b.0.unsignedScaleFactor=1.0
unit.0.0.port.5.b.0.visible=1
unit.0.0.port.5.buscount=1
unit.0.0.port.5.channelcount=6
unit.0.0.port.5.s.0.alias=SPI_state0
unit.0.0.port.5.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.5.s.0.name=TriggerPort5[0]
unit.0.0.port.5.s.0.orderindex=-1
unit.0.0.port.5.s.0.visible=1
unit.0.0.port.5.s.1.alias=SPI_state1
unit.0.0.port.5.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.5.s.1.name=TriggerPort5[1]
unit.0.0.port.5.s.1.orderindex=-1
unit.0.0.port.5.s.1.visible=1
unit.0.0.port.5.s.2.alias=SPI_state2
unit.0.0.port.5.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.5.s.2.name=TriggerPort5[2]
unit.0.0.port.5.s.2.orderindex=-1
unit.0.0.port.5.s.2.visible=1
unit.0.0.port.5.s.3.alias=SPI_state3
unit.0.0.port.5.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.5.s.3.name=TriggerPort5[3]
unit.0.0.port.5.s.3.orderindex=-1
unit.0.0.port.5.s.3.visible=1
unit.0.0.port.5.s.4.alias=SPI_state4
unit.0.0.port.5.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.5.s.4.name=TriggerPort5[4]
unit.0.0.port.5.s.4.orderindex=-1
unit.0.0.port.5.s.4.visible=1
unit.0.0.port.5.s.5.alias=SPI_state5
unit.0.0.port.5.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.5.s.5.name=TriggerPort5[5]
unit.0.0.port.5.s.5.orderindex=-1
unit.0.0.port.5.s.5.visible=1
unit.0.0.portcount=6
unit.0.0.rep_trigger.clobber=1
unit.0.0.rep_trigger.dir=D\:\\03_FPGA_Project\\01_UAV_CMOS\\02_FPGA\\UAV_CMOS\\UAV_CMOS
unit.0.0.rep_trigger.filename=waveform
unit.0.0.rep_trigger.format=ASCII
unit.0.0.rep_trigger.loggingEnabled=0
unit.0.0.rep_trigger.signals=All Signals/Buses
unit.0.0.samplesPerTrigger=1
unit.0.0.triggerCapture=1
unit.0.0.triggerNSamplesTS=0
unit.0.0.triggerPosition=0
unit.0.0.triggerWindowCount=1
unit.0.0.triggerWindowDepth=1024
unit.0.0.triggerWindowTS=0
unit.0.0.username=MyILA0
unit.0.0.waveform.count=11
unit.0.0.waveform.posn.0.channel=2147483646
unit.0.0.waveform.posn.0.name=data_read
unit.0.0.waveform.posn.0.radix=1
unit.0.0.waveform.posn.0.type=bus
unit.0.0.waveform.posn.1.channel=2147483646
unit.0.0.waveform.posn.1.name=data_read_shift
unit.0.0.waveform.posn.1.radix=1
unit.0.0.waveform.posn.1.type=bus
unit.0.0.waveform.posn.10.channel=2147483646
unit.0.0.waveform.posn.10.name=SPI_BUS_COUNTER
unit.0.0.waveform.posn.10.radix=4
unit.0.0.waveform.posn.10.type=bus
unit.0.0.waveform.posn.11.channel=43
unit.0.0.waveform.posn.11.name=sclk_buf
unit.0.0.waveform.posn.11.type=signal
unit.0.0.waveform.posn.2.channel=0
unit.0.0.waveform.posn.2.name=Reset
unit.0.0.waveform.posn.2.radix=1
unit.0.0.waveform.posn.2.type=signal
unit.0.0.waveform.posn.3.channel=1
unit.0.0.waveform.posn.3.name=execute_Pulse
unit.0.0.waveform.posn.3.type=signal
unit.0.0.waveform.posn.4.channel=2
unit.0.0.waveform.posn.4.name=SS_N
unit.0.0.waveform.posn.4.type=signal
unit.0.0.waveform.posn.5.channel=3
unit.0.0.waveform.posn.5.name=SCLK
unit.0.0.waveform.posn.5.type=signal
unit.0.0.waveform.posn.6.channel=43
unit.0.0.waveform.posn.6.name=sclk_buf
unit.0.0.waveform.posn.6.radix=1
unit.0.0.waveform.posn.6.type=signal
unit.0.0.waveform.posn.7.channel=4
unit.0.0.waveform.posn.7.name=MOSI
unit.0.0.waveform.posn.7.radix=1
unit.0.0.waveform.posn.7.type=signal
unit.0.0.waveform.posn.8.channel=5
unit.0.0.waveform.posn.8.name=MISO
unit.0.0.waveform.posn.8.radix=1
unit.0.0.waveform.posn.8.type=signal
unit.0.0.waveform.posn.9.channel=2147483646
unit.0.0.waveform.posn.9.name=SPI_state
unit.0.0.waveform.posn.9.radix=1
unit.0.0.waveform.posn.9.type=bus

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS.cmd_log Normal file
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vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/SPI_BUS.v -lang verilog -prj UAV_CMOS -o SPI_BUS.spl -module SPI_BUS -template d:/01_Installed_SW/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6 SPI_BUS.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/SPI_BUS.sym
vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/SPI_BUS.v -lang verilog -prj UAV_CMOS -o SPI_BUS.spl -module SPI_BUS -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l SPI_BUS.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/SPI_BUS.sym

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS.fdo Normal file
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######################################################################
##
## Filename: SPI_BUS.fdo
## Created on: Tue Sep 05 10:27:29 PM China Standard Time 2017
##
## Auto generated by Project Navigator for Behavioral Simulation
##
## ---------------------DO NOT EDIT THIS FILE-------------------------
## You may want to add additional commands to control the simulation
## in the user specific do file (<module>.udo) which is automatically
## generated in the project directory and will not be removed on
## subsequent simulation flows run from Project Navigator.
## ---------------------DO NOT EDIT THIS FILE-------------------------
##
######################################################################
#
# Create work library
#
vlib work
#
# Compile sources
#
vlog "SPI_BUS.v"
vlog "d:/01_Installed_SW/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ps -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work work.SPI_BUS glbl
#
# Source the wave do file
#
do {SPI_BUS_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {SPI_BUS.udo}
#
# Run simulation for this time
#
run 300ns
#
# End
#

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS.lso Normal file
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work

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="SPI_BUS">
<symboltype>BLOCK</symboltype>
<timestamp>2017-9-20T13:7:39</timestamp>
<attr value="SPI_BUS" name="VeriModel" />
<pin polarity="Input" x="0" y="-336" name="reset" />
<pin polarity="Input" x="0" y="-272" name="clk_input" />
<pin polarity="Output" x="672" y="-336" name="SCLK" />
<pin polarity="Output" x="672" y="-272" name="SS_N" />
<pin polarity="Input" x="0" y="-208" name="MISO" />
<pin polarity="Output" x="672" y="-144" name="spi_idle_fd" />
<pin polarity="Output" x="672" y="-208" name="MOSI" />
<pin polarity="Input" x="0" y="-128" name="execute_pulse" />
<pin polarity="Output" x="672" y="-80" name="read_latch" />
<pin polarity="Input" x="0" y="-16" name="data_write(15:0)" />
<pin polarity="Input" x="0" y="48" name="command_address(9:0)" />
<pin polarity="Output" x="672" y="-16" name="data_read(15:0)" />
<pin polarity="Output" x="672" y="48" name="command_read(9:0)" />
<graph>
<rect width="544" x="64" y="-384" height="468" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-336" type="pin reset" />
<line x2="0" y1="-336" y2="-336" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-272" type="pin clk_input" />
<line x2="0" y1="-272" y2="-272" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="600" y="-336" type="pin SCLK" />
<line x2="672" y1="-336" y2="-336" x1="608" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="600" y="-272" type="pin SS_N" />
<line x2="672" y1="-272" y2="-272" x1="608" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-208" type="pin MISO" />
<line x2="0" y1="-208" y2="-208" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="600" y="-144" type="pin spi_idle_fd" />
<line x2="672" y1="-144" y2="-144" x1="608" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="600" y="-208" type="pin MOSI" />
<line x2="672" y1="-208" y2="-208" x1="608" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="360" y="-384" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-128" type="pin execute_pulse" />
<line x2="0" y1="-128" y2="-128" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="600" y="-80" type="pin read_latch" />
<line x2="672" y1="-80" y2="-80" x1="608" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-16" type="pin data_write(15:0)" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="48" type="pin command_address(9:0)" />
<rect width="64" x="0" y="-28" height="24" />
<line x2="0" y1="-16" y2="-16" x1="64" />
<rect width="64" x="0" y="36" height="24" />
<line x2="0" y1="48" y2="48" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="600" y="-16" type="pin data_read(15:0)" />
<rect width="64" x="608" y="-28" height="24" />
<line x2="672" y1="-16" y2="-16" x1="608" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="600" y="48" type="pin command_read(9:0)" />
<rect width="64" x="608" y="36" height="24" />
<line x2="672" y1="48" y2="48" x1="608" />
</graph>
</symbol>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS.udo Normal file
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######################################################################
##
## Filename: SPI_BUS.udo
## Created on: Tue Sep 05 10:27:29 PM China Standard Time 2017
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06:06:38 09/05/2017
// Design Name:
// Module Name: SPI_BUS
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_BUS(
clk_input,
SCLK,SS_N,MOSI,MISO,
data_write,data_read,
command_address,
command_read,read_latch,
reset,spi_idle_fd,
execute_pulse
);
input clk_input ;
input [15:0]data_write ;
input [9:0]command_address;
output [15:0]data_read ;
output [9:0]command_read ;
output SCLK,SS_N,MOSI ;
output spi_idle_fd ;
output read_latch ;
input MISO ;
input reset ;
input execute_pulse ;
parameter
SPI_bus_busy = 4'b0001 ,
SPI_bus_start = 4'b0010 ,
SPI_bus_stop = 4'b0100 ,
SPI_bus_idle = 4'b1000 ;
parameter
SPI_idle = 6'b000000,
SPI_waite = 6'b000010,
SPI_address = 6'b000100,
SPI_data_write = 6'b001000,
SPI_data_read = 6'b010000,
SPI_stop = 6'b100000,
SPI_read_wait = 6'b000001;
reg [3:0]SPI_bus_state ;
reg [5:0]SPI_state ;
reg [5:0]next_SPI_state ;
reg [4:0]SPI_bus_counter;
reg read_latch ;
reg read_latch_buf ;
reg sclk_buf ;
reg SCLK ;
reg SS_N ;
reg MOSI ;
reg [15:0]data_read ;
reg [9:0]command_read ;
reg [15:0]data_read_buf ;
reg [15:0]data_write_buf;
reg [9:0]command_address_buf;
reg execute_pulse_buf ;
reg [15:0]data_write_shift;
reg [15:0]data_read_shift ;
reg [9:0]command_address_shift;
reg MISO_buf ;
reg spi_read_flag ;
reg spi_read_flag_buf1 ;
reg spi_read_flag_buf2 ;
reg spi_idle_fd ;
reg spi_idle_fd_flag ;
reg spi_idle_fd_flag_buf1;
reg spi_idle_fd_flag_buf2;
always @ ( posedge clk_input or posedge reset )
begin
if ( reset )
begin
read_latch_buf <= 0 ;
read_latch <= 0 ;
spi_read_flag <= 0 ;
spi_read_flag_buf1 <= 0 ;
spi_read_flag_buf2 <= 0 ;
end
else
begin
if ( SPI_state == SPI_data_read )
begin
spi_read_flag <= 1 ;
end
else
begin
spi_read_flag <= 0 ;
end
spi_read_flag_buf1 <= spi_read_flag ;
spi_read_flag_buf2 <= spi_read_flag_buf1 ;
read_latch_buf <= ( spi_read_flag_buf2 ) && ( ~spi_read_flag_buf1 ) ;
read_latch <= read_latch_buf ;
end
end
always @ ( posedge clk_input or posedge reset )
begin
if ( reset == 1 )
begin
spi_idle_fd <= 1 ;
spi_idle_fd_flag <= 1 ;
spi_idle_fd_flag_buf1 <= 1 ;
spi_idle_fd_flag_buf2 <= 1 ;
end
else
begin
if ( SPI_state == SPI_idle )
begin
spi_idle_fd_flag <= 1 ;
end
else
begin
spi_idle_fd_flag <= 0 ;
end
spi_idle_fd_flag_buf1 <= spi_idle_fd_flag ;
spi_idle_fd_flag_buf2 <= spi_idle_fd_flag_buf1 ;
spi_idle_fd <= ( ~spi_idle_fd_flag_buf2 ) && ( spi_idle_fd_flag_buf1 ) ;
end
end
always @ ( posedge clk_input or posedge reset )
begin
if ( reset )
begin
MISO_buf <= 0 ;
end
else
begin
MISO_buf <= MISO ;
end
end
always @ ( posedge clk_input or posedge reset )
begin
if ( reset )
begin
data_write_buf <= 0 ;
command_address_buf <= 0 ;
execute_pulse_buf <= 0 ;
end
else
begin
data_write_buf <= data_write ;
command_address_buf <= command_address ;
execute_pulse_buf <= execute_pulse ;
end
end
always @ ( posedge clk_input or posedge reset )
begin
if ( reset )
begin
SPI_bus_counter <= 0 ;
end
else
if ( SPI_bus_state == SPI_bus_idle )
begin
SPI_bus_counter <= 0 ;
end
else
if ( SPI_bus_counter == 31 )
begin
SPI_bus_counter <= SPI_bus_counter ;
end
else
begin
SPI_bus_counter <=SPI_bus_counter + sclk_buf ;
end
end
always @ ( posedge clk_input or posedge reset )
begin
if ( reset )
begin
sclk_buf <= 0 ;
end
else
if ( SPI_bus_state != SPI_bus_idle )
begin
sclk_buf <= ~sclk_buf;
end
else
begin
sclk_buf <= 0 ;
end
end
always @ ( posedge clk_input or posedge reset )
begin
if ( reset )
begin
SCLK <= 0 ;
SS_N <= 1 ;
SPI_bus_state <= SPI_bus_idle;
end
else
begin
case ( SPI_bus_state )
SPI_bus_idle :
begin
SCLK <= 0 ;
SS_N <= 1 ;
if ( execute_pulse_buf )
SPI_bus_state <= SPI_bus_start ;
end
SPI_bus_start:
begin
if ( SPI_bus_counter == 1 )
begin
SS_N <= 0 ;
end
else
if ( SPI_bus_counter == 2 )
begin
SPI_bus_state <= SPI_bus_busy ;
end
end
SPI_bus_busy :
begin
if ( SPI_bus_counter == 28 )
begin
SCLK <= 0 ;
SPI_bus_state <= SPI_bus_stop;
end
else
begin
SCLK <= sclk_buf ;
end
end
SPI_bus_stop :
begin
if ( SPI_bus_counter == 30 )
begin
SS_N <= 1 ;
end
else
if ( SPI_bus_counter == 31 )
begin
SPI_bus_state <= SPI_bus_idle;
end
end
default :
begin
SPI_bus_state <= SPI_bus_idle;
SS_N <= 1 ;
SCLK <= 0 ;
end
endcase
end
end
always @ ( posedge clk_input or posedge reset )
begin
if ( reset )
begin
SPI_state <= SPI_idle ;
next_SPI_state <= SPI_idle ;
MOSI <= 0 ;
data_read <= 0 ;
data_write_shift <= 0 ;
command_address_shift <= 0 ;
data_read_shift <= 0 ;
command_read <= 0 ;
end
else
begin
case ( SPI_state )
SPI_idle :
begin
if ( execute_pulse_buf )
begin
SPI_state <= SPI_waite ;
end
data_write_shift <= data_write_buf ;
command_read <= command_address_buf ;
command_address_shift <= command_address_buf ;
end
SPI_waite :
begin
if ( command_address_shift[0] )
begin
next_SPI_state <= SPI_data_write ;
end
else
begin
next_SPI_state <= SPI_read_wait ;
end
if ( SPI_bus_counter == 1 )
begin
SPI_state <= SPI_address ;
end
end
SPI_address :
begin
if ( SPI_bus_counter == 11 )
begin
SPI_state <= next_SPI_state ;
end
if ( sclk_buf == 0 )
begin
MOSI <= command_address_shift[9] ;
command_address_shift[9:0] <= {command_address_shift[8:0],1'b0};
end
end
SPI_data_write:
begin
if ( SPI_bus_counter == 27 )
begin
SPI_state <= SPI_stop ;
end
if ( sclk_buf == 0 )
begin
MOSI <= data_write_shift[15] ;
data_write_shift[15:0] <= {data_write_shift[14:0],1'b0};
end
end
SPI_read_wait :
begin
if ( SPI_bus_counter == 13 )
begin
SPI_state <= SPI_data_read ;
end
end
SPI_data_read :
begin
if ( SPI_bus_counter == 29 )
begin
SPI_state <= SPI_stop ;
end
if ( sclk_buf == 0 )
begin
data_read_shift[0] <= MISO_buf;
data_read_shift[15:1] <= data_read_shift[14:0];
end
end
SPI_stop :
begin
//data_read_buf <= data_read_shift ;
if ( sclk_buf == 0 )
begin
MOSI <= 0 ;
data_read_buf <= data_read_shift ;
end
if ( SPI_bus_counter == 31 )
begin
SPI_state <= SPI_idle ;
data_read <= data_read_buf ;
end
end
default :
begin
SPI_state <= SPI_idle ;
next_SPI_state <= SPI_idle ;
MOSI <= 0 ;
data_read <= 0 ;
data_write_shift <= 0 ;
command_address_shift <= 0 ;
data_read_shift <= 0 ;
end
endcase
end
end
endmodule

50
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS_Test.fdo Normal file
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@ -0,0 +1,50 @@
######################################################################
##
## Filename: SPI_BUS_Test.fdo
## Created on: Tue Sep 05 10:35:38 PM China Standard Time 2017
##
## Auto generated by Project Navigator for Behavioral Simulation
##
## ---------------------DO NOT EDIT THIS FILE-------------------------
## You may want to add additional commands to control the simulation
## in the user specific do file (<module>.udo) which is automatically
## generated in the project directory and will not be removed on
## subsequent simulation flows run from Project Navigator.
## ---------------------DO NOT EDIT THIS FILE-------------------------
##
######################################################################
#
# Create work library
#
vlib work
#
# Compile sources
#
vlog "SPI_BUS.v"
vlog "SPI_BUS_Test.v"
vlog "d:/01_Installed_SW/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ps -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work work.SPI_BUS_Test glbl
#
# Source the wave do file
#
do {SPI_BUS_Test_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {SPI_BUS_Test.udo}
#
# Run simulation for this time
#
run 300ns
#
# End
#

10
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS_Test.udo Normal file
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@ -0,0 +1,10 @@
######################################################################
##
## Filename: SPI_BUS_Test.udo
## Created on: Tue Sep 05 9:47:12 PM China Standard Time 2017
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################

82
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS_Test.v Normal file
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@ -0,0 +1,82 @@
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:40:59 09/05/2017
// Design Name: SPI_BUS
// Module Name: D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/SPI_BUS_Test.v
// Project Name: UAV_CMOS
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: SPI_BUS
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SPI_BUS_Test;
// Inputs
reg clk_input;
reg MISO;
reg [15:0] data_write;
reg [9:0] command_address;
reg reset;
reg execute_pulse;
// Outputs
wire SCLK;
wire SS_N;
wire MOSI;
wire [15:0] data_read;
// Instantiate the Unit Under Test (UUT)
SPI_BUS uut (
.clk_input(clk_input),
.SCLK(SCLK),
.SS_N(SS_N),
.MOSI(MOSI),
.MISO(MISO),
.data_write(data_write),
.data_read(data_read),
.command_address(command_address),
.reset(reset),
.execute_pulse(execute_pulse)
);
initial begin
// Initialize Inputs
clk_input = 0;
MISO = 0;
data_write = 0;
command_address = 0;
reset = 0;
execute_pulse = 0;
// Wait 100 ns for global reset to finish
#10;
#1 reset = 1 ;
#5 reset = 0 ;
// Add stimulus here
#2 command_address = 10'b1100110011 ;
data_write = 16'hAAAA;
#3 execute_pulse = 1 ;
#3 execute_pulse = 0 ;
#180
#2 command_address = 10'b1100110010 ;
MISO = 1 ;
#3 execute_pulse = 1 ;
#3 execute_pulse = 0 ;
end
always #1 clk_input = ~ clk_input ;
endmodule

12
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS_Test_wave.fdo Normal file
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@ -0,0 +1,12 @@
######################################################################
##
## Filename: SPI_BUS_Test_wave.fdo
## Created on: Tue Sep 05 9:47:13 PM China Standard Time 2017
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
add wave /glbl/GSR

12
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/SPI_BUS_wave.fdo Normal file
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@ -0,0 +1,12 @@
######################################################################
##
## Filename: SPI_BUS_wave.fdo
## Created on: Tue Sep 05 10:27:29 PM China Standard Time 2017
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
add wave /glbl/GSR

262
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/UAV_CMOS.gise Normal file
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@ -0,0 +1,262 @@
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<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="main.jhd"/>
<outfile xil_pn:name="main.lso"/>
<outfile xil_pn:name="main.ngc"/>
<outfile xil_pn:name="main.ngr"/>
<outfile xil_pn:name="main.prj"/>
<outfile xil_pn:name="main.stx"/>
<outfile xil_pn:name="main.syr"/>
<outfile xil_pn:name="main.xst"/>
<outfile xil_pn:name="main_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1510024432" xil_pn:in_ck="-5335026897010909130" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="123229027435927655" xil_pn:start_ts="1510024432">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1510024452" xil_pn:in_ck="3265349925345657504" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-8534279615741686869" xil_pn:start_ts="1510024432">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="main.bld"/>
<outfile xil_pn:name="main.ngd"/>
<outfile xil_pn:name="main_cs.blc"/>
<outfile xil_pn:name="main_cs.ngc"/>
<outfile xil_pn:name="main_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1510024525" xil_pn:in_ck="-7658983018958932395" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2368679570676750054" xil_pn:start_ts="1510024452">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="main.pcf"/>
<outfile xil_pn:name="main_map.map"/>
<outfile xil_pn:name="main_map.mrp"/>
<outfile xil_pn:name="main_map.ncd"/>
<outfile xil_pn:name="main_map.ngm"/>
<outfile xil_pn:name="main_map.xrpt"/>
<outfile xil_pn:name="main_summary.xml"/>
<outfile xil_pn:name="main_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1510024592" xil_pn:in_ck="6620140989429721070" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-8069197479544554484" xil_pn:start_ts="1510024525">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="main.ncd"/>
<outfile xil_pn:name="main.pad"/>
<outfile xil_pn:name="main.par"/>
<outfile xil_pn:name="main.ptwx"/>
<outfile xil_pn:name="main.unroutes"/>
<outfile xil_pn:name="main.xpi"/>
<outfile xil_pn:name="main_pad.csv"/>
<outfile xil_pn:name="main_pad.txt"/>
<outfile xil_pn:name="main_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1510024617" xil_pn:in_ck="4774924121320" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1510024592">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="main.bgn"/>
<outfile xil_pn:name="main.bit"/>
<outfile xil_pn:name="main.drc"/>
<outfile xil_pn:name="main.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1509974085" xil_pn:in_ck="4774924108466" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="-5324886243551662533" xil_pn:start_ts="1509974080">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1510024729" xil_pn:in_ck="4774924108466" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="7525096600467727589" xil_pn:start_ts="1510024617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1509921479" xil_pn:in_ck="4774924108466" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-8534279615741686869" xil_pn:start_ts="1509921479">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1510024592" xil_pn:in_ck="-7658983018958932527" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1510024581">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="main.twr"/>
<outfile xil_pn:name="main.twx"/>
</transform>
</transforms>
</generated_project>

413
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/UAV_CMOS.ucf Normal file
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NET "CMOS_CLK" LOC = V10;
NET "usb_reset_out" LOC = M13;
#NET "key" LOC = N4;
NET "SPI_MISO" LOC = B14;
NET "SPI_MOSI" LOC = A14;
NET "SPI_CLK" LOC = A15;
NET "SPI_SS" LOC = A13;
NET "reset" LOC = B12;
NET "cmos_pll" LOC = C13;
NET "LVDS_DATA_0_P" LOC = G9;
NET "LVDS_DATA_0_N" LOC = F9;
#NET "LVDS_DATA_1_P" LOC = D14;
#NET "LVDS_DATA_1_N" LOC = C14;
#NET "LVDS_DATA_2_P" LOC = B16;
#NET "LVDS_DATA_2_N" LOC = A16;
#NET "LVDS_DATA_3_P" LOC = B11;
#NET "LVDS_DATA_3_N" LOC = A11;
NET "LVDS_SYNC_P" LOC = C10;
NET "LVDS_SYNC_N" LOC = A10;
NET "LVDS_CLK_P" LOC = D11;
NET "LVDS_CLK_N" LOC = C11;
NET "LVDS_DATA_0_P" DIFF_TERM = "TRUE";
NET "LVDS_DATA_0_N" DIFF_TERM = "TRUE";
#NET "LVDS_DATA_1_P" DIFF_TERM = TRUE;
#NET "LVDS_DATA_1_N" DIFF_TERM = TRUE;
#NET "LVDS_DATA_2_P" DIFF_TERM = TRUE;
#NET "LVDS_DATA_2_N" DIFF_TERM = TRUE;
#NET "LVDS_DATA_3_P" DIFF_TERM = TRUE;
#NET "LVDS_DATA_3_N" DIFF_TERM = TRUE;
NET "LVDS_SYNC_P" DIFF_TERM = "TRUE";
NET "LVDS_SYNC_N" DIFF_TERM = "TRUE";
NET "LVDS_CLK_P" DIFF_TERM = "TRUE";
NET "LVDS_CLK_N" DIFF_TERM = "TRUE";
NET "cmos_triger0" LOC = B8;
NET "cmos_triger1" LOC = A8;
NET "cmos_triger2" LOC = A9;
NET "cmos_monitor[0]" LOC = B9;
NET "cmos_monitor[1]" LOC = A12;
#NET "Test_point13" LOC = D6;
#NET "Test_point9" LOC = A3;
NET "XLXN_1554" LOC = B3;
NET "XLXN_1554" IOSTANDARD = LVCMOS33;
#NET "clk_50m" LOC = C8;
#NET "clk_50m" IOSTANDARD = LVCMOS33;
#PIN "XLXI_563/mig_39_2_inst/memc3_infrastructure_inst/U_BUFG_CLK3.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "USB_FlagA" LOC = E18;
NET "USB_FlagB" LOC = F18;
NET "USB_FlagC" LOC = G18;
NET "USB_FlagD" LOC = K18;
NET "USB_SLWR" LOC = N16;
NET "USB_SLRD" LOC = M16;
NET "USB_SLOE" LOC = H18;
NET "USB_SCLK" LOC = K17;
NET "USB_PKTEND" LOC = J18;
NET "LED" LOC = U3;
#Created by Constraints Editor (xc6slx45l-csg324-1l) - 2017/09/15
NET "CMOS_CLK" TNM_NET = "CMOS_CLK";
TIMESPEC TS_CMOS_CLK = PERIOD "CMOS_CLK" 60 MHz HIGH 50 %;
NET "USB_SCLK" TNM_NET = "USB_SCLK";
TIMESPEC TS_USB_SCLK = PERIOD "USB_SCLK" 55 MHz HIGH 50 %;
NET "USB_SCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "XLXI_120/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "XLXN_934" TNM_NET = "XLXN_934";
#TIMESPEC TS_XLXN_934 = PERIOD "XLXN_934" 250 MHz HIGH 50 %;
#######################################
INST "XLXI_30/USB_Data_in_buf_0" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_1" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_2" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_3" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_4" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_5" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_6" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_7" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_8" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_9" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_10" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_11" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_12" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_13" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_14" IOB =TRUE;
INST "XLXI_30/USB_Data_in_buf_15" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_0" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_1" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_2" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_3" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_4" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_5" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_6" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_7" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_8" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_9" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_10" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_11" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_12" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_13" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_14" IOB =TRUE;
INST "XLXI_30/USB_Data_out_buf_15" IOB =TRUE;
INST "USB_FIFOADR_0_OBUF" IOB =TRUE;
##Created by Constraints Editor (xc6slx45l-csg324-1l) - 2017/09/16
#NET "XLXI_30/USB_DATA<0>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<1>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<2>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<3>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<4>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<5>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<6>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<7>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<8>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<9>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<10>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<11>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<12>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<13>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<14>" TNM = USB_DATA;
#NET "XLXI_30/USB_DATA<15>" TNM = USB_DATA;
#INST "XLXI_30/USB_Data_in_buf_0" TNM = USB_Data_in_buf_0;
#INST "XLXI_30/USB_Data_in_buf_1" TNM = USB_Data_in_buf_1;
#INST "XLXI_30/USB_Data_in_buf_2" TNM = USB_Data_in_buf_2;
#INST "XLXI_30/USB_Data_in_buf_3" TNM = USB_Data_in_buf_3;
#INST "XLXI_30/USB_Data_in_buf_4" TNM = USB_Data_in_buf_4;
#INST "XLXI_30/USB_Data_in_buf_5" TNM = USB_Data_in_buf_5;
#INST "XLXI_30/USB_Data_in_buf_6" TNM = USB_Data_in_buf_6;
#INST "XLXI_30/USB_Data_in_buf_7" TNM = USB_Data_in_buf_7;
#INST "XLXI_30/USB_Data_in_buf_8" TNM = USB_Data_in_buf_8;
#INST "XLXI_30/USB_Data_in_buf_9" TNM = USB_Data_in_buf_9;
#INST "XLXI_30/USB_Data_in_buf_10" TNM = USB_Data_in_buf_10;
#INST "XLXI_30/USB_Data_in_buf_11" TNM = USB_Data_in_buf_11;
#INST "XLXI_30/USB_Data_in_buf_12" TNM = USB_Data_in_buf_12;
#INST "XLXI_30/USB_Data_in_buf_13" TNM = USB_Data_in_buf_13;
#INST "XLXI_30/USB_Data_in_buf_14" TNM = USB_Data_in_buf_14;
#INST "XLXI_30/USB_Data_in_buf_15" TNM = USB_Data_in_buf_15;
#NET "USB_DATA<0>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_0" RISING;
#NET "USB_DATA<1>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_1" RISING;
#NET "USB_DATA<2>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_2" RISING;
#NET "USB_DATA<3>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_3" RISING;
#NET "USB_DATA<4>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_4" RISING;
#NET "USB_DATA<5>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_5" RISING;
#NET "USB_DATA<6>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_6" RISING;
#NET "USB_DATA<7>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_7" RISING;
#NET "USB_DATA<8>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_8" RISING;
#NET "USB_DATA<9>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_9" RISING;
#NET "USB_DATA<10>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_10" RISING;
#NET "USB_DATA<11>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_11" RISING;
#NET "USB_DATA<12>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_12" RISING;
#NET "USB_DATA<13>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_13" RISING;
#NET "USB_DATA<14>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_14" RISING;
#NET "USB_DATA<15>" OFFSET = IN 10 ns VALID 18.1818 ns BEFORE "USB_SCLK" TIMEGRP "USB_Data_in_buf_15" RISING;
#Created by Constraints Editor (xc6slx45l-csg324-1l) - 2017/09/16
#NET "USB_DATA[0]" TIG = TS_USB_SCLK;
#NET "USB_DATA[1]" TIG = TS_USB_SCLK;
#NET "USB_DATA[2]" TIG = TS_USB_SCLK;
#NET "USB_DATA[3]" TIG = TS_USB_SCLK;
#NET "USB_DATA[4]" TIG = TS_USB_SCLK;
#NET "USB_DATA[5]" TIG = TS_USB_SCLK;
#NET "USB_DATA[6]" TIG = TS_USB_SCLK;
#NET "USB_DATA[7]" TIG = TS_USB_SCLK;
#NET "USB_DATA[8]" TIG = TS_USB_SCLK;
#NET "USB_DATA[9]" TIG = TS_USB_SCLK;
#NET "USB_DATA[10]" TIG = TS_USB_SCLK;
#NET "USB_DATA[11]" TIG = TS_USB_SCLK;
#NET "USB_DATA[12]" TIG = TS_USB_SCLK;
#NET "USB_DATA[13]" TIG = TS_USB_SCLK;
#NET "USB_DATA[14]" TIG = TS_USB_SCLK;
#NET "USB_DATA[15]" TIG = TS_USB_SCLK;
#pin2ucf - Wed Sep 27 19:25:06 2017
#The following constraints were newly added
NET "USB_DATA[11]" LOC = N15;
NET "USB_DATA[5]" LOC = H14;
NET "USB_DATA[12]" LOC = M18;
NET "USB_DATA[6]" LOC = G13;
NET "USB_DATA[13]" LOC = H12;
NET "USB_DATA[7]" LOC = F17;
NET "XLXN_538" LOC = T12;
NET "USB_DATA[14]" LOC = N17;
NET "USB_DATA[8]" LOC = L17;
NET "USB_DATA[15]" LOC = H13;
NET "USB_DATA[9]" LOC = K13;
#NET "XLXN_92[0]" LOC = R15;
#NET "XLXN_750" LOC = T11;
#NET "XLXN_751" LOC = R11;
#NET "XLXN_746" LOC = M10;
#NET "XLXN_752" LOC = V12;
#NET "XLXN_92[1]" LOC = T15;
#NET "XLXN_747" LOC = U11;
#NET "XLXN_753" LOC = N10;
#NET "XLXN_748" LOC = V11;
#NET "XLXN_754" LOC = N9;
#NET "XLXN_749" LOC = U10;
#NET "XLXN_755" LOC = T10;
#NET "XLXN_92[2]" LOC = U16;
#NET "XLXN_92[3]" LOC = V16;
#NET "XLXN_92[4]" LOC = R13;
#NET "XLXN_92[5]" LOC = T13;
#NET "XLXN_92[6]" LOC = U15;
#NET "XLXN_92[7]" LOC = V15;
#NET "XLXN_92[8]" LOC = T14;
#NET "XLXN_92[9]" LOC = V14;
#NET "XLXN_92[10]" LOC = N12;
#NET "XLXN_92[11]" LOC = P12;
#NET "XLXN_92[12]" LOC = U13;
#NET "XLXN_92[13]" LOC = V13;
#NET "XLXN_92[14]" LOC = M11;
NET "USB_FIFOADR[0]" LOC = H15;
#NET "XLXN_92[15]" LOC = N11;
NET "USB_FIFOADR[1]" LOC = K12;
NET "USB_DATA[0]" LOC = D17;
NET "USB_DATA[1]" LOC = H16;
NET "USB_DATA[2]" LOC = D18;
NET "USB_DATA[3]" LOC = G16;
NET "USB_DATA[10]" LOC = L18;
NET "USB_DATA[4]" LOC = E16;
NET "XLXN_538" PULLDOWN;
#PIN "clk_cmos_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45l-csg324-1l) - 2017/10/21
NET "LVDS_CLK_N" TNM_NET = "LVDS_CLK_N";
TIMESPEC TS_LVDS_CLK_N = PERIOD "LVDS_CLK_N" 4 ns HIGH 50 %;
NET "LVDS_CLK_P" TNM_NET = "LVDS_CLK_P";
#TIMESPEC TS_LVDS_CLK_P = PERIOD "LVDS_CLK_P" 4 ns HIGH 50 %;
#PIN "XLXI_324/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
# PlanAhead Generated IO constraints
NET "LVDS_CLK_P" IOSTANDARD = LVDS_33;
NET "LVDS_CLK_N" IOSTANDARD = LVDS_33;
NET "LVDS_DATA_0_P" IOSTANDARD = LVDS_33;
NET "LVDS_DATA_0_N" IOSTANDARD = LVDS_33;
NET "LVDS_SYNC_P" IOSTANDARD = LVDS_33;
NET "LVDS_SYNC_N" IOSTANDARD = LVDS_33;
NET "cmos_monitor[1]" IOSTANDARD = LVCMOS33;
NET "cmos_monitor[0]" IOSTANDARD = LVCMOS33;
NET "reset" IOSTANDARD = LVCMOS33;
NET "SPI_CLK" IOSTANDARD = LVCMOS33;
NET "SPI_MISO" IOSTANDARD = LVCMOS33;
NET "cmos_triger2" IOSTANDARD = LVCMOS33;
NET "cmos_triger1" IOSTANDARD = LVCMOS33;
NET "cmos_triger0" IOSTANDARD = LVCMOS33;
NET "CMOS_CLK" IOSTANDARD = LVCMOS33;
NET "cmos_pll" IOSTANDARD = LVCMOS33;
#NET "key" IOSTANDARD = LVCMOS25;
NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
NET "SPI_SS" IOSTANDARD = LVCMOS33;
###############################################
##NET "clk_cmos" LOC = D8;
#NET "XLXN_1247" LOC = B6;
#NET "XLXN_1248" LOC = B4;
#NET "XLXN_1247" IOSTANDARD = LVCMOS33;
#NET "XLXN_1248" IOSTANDARD = LVCMOS33;
CONFIG VCCAUX=3.3; # Valid values are 2.5 and 3.3
############################################################################
# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
# follows the corresponding GUI option setting. However, DDR3 can operate at higher
# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
# remove/edit the below constraint to avoid false errors.
############################################################################
CONFIG MCB_PERFORMANCE= EXTENDED;
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
#NET "XLXI_563/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
##NET "c?_pll_lock" TIG;
#INST "XLXI_563/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#Please uncomment the below TIG if used in a design which enables self-refresh mode
#NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
############################################################################
## Clock constraints
############################################################################
#NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
#TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 20 ns HIGH 50 %;
############################################################################
##reset
############################################################################
#NET "reset_n" LOC = N4 | IOSTANDARD = "LVCMOS15"; ## SW2 pushbutton
############################################################################
## Memory Controller 3
## Memory Device: DDR3_SDRAM->MT41J128M16XX-187E
## Frequency: 312.5 MHz
## Time Period: 3200 ps
## Supported Part Numbers: MT41J128M16HA-187E
############################################################################
############################################################################
## I/O TERMINATION
############################################################################
NET "mcb3_dram_dq[*]" IN_TERM = NONE;
NET "mcb3_dram_dqs" IN_TERM = NONE;
NET "mcb3_dram_dqs_n" IN_TERM = NONE;
NET "mcb3_dram_udqs" IN_TERM = NONE;
NET "mcb3_dram_udqs_n" IN_TERM = NONE;
############################################################################
# I/O STANDARDS
############################################################################
NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_a[*]" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_cke" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_ras_n" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_cas_n" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_we_n" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_odt" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_reset_n" IOSTANDARD = LVCMOS15 ;
NET "mcb3_dram_dm" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_dram_udm" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_rzq" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
NET "mcb3_zio" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
NET "mcb3_dram_a[0]" LOC = "J7" ;
NET "mcb3_dram_a[10]" LOC = "F4" ;
NET "mcb3_dram_a[11]" LOC = "D3" ;
NET "mcb3_dram_a[12]" LOC = "G6" ;
NET "mcb3_dram_a[13]" LOC = "F6" ;
NET "mcb3_dram_a[1]" LOC = "J6" ;
NET "mcb3_dram_a[2]" LOC = "H5" ;
NET "mcb3_dram_a[3]" LOC = "L7" ;
NET "mcb3_dram_a[4]" LOC = "F3" ;
NET "mcb3_dram_a[5]" LOC = "H4" ;
NET "mcb3_dram_a[6]" LOC = "H3" ;
NET "mcb3_dram_a[7]" LOC = "H6" ;
NET "mcb3_dram_a[8]" LOC = "D2" ;
NET "mcb3_dram_a[9]" LOC = "D1" ;
NET "mcb3_dram_ba[0]" LOC = "F2" ;
NET "mcb3_dram_ba[1]" LOC = "F1" ;
NET "mcb3_dram_ba[2]" LOC = "E1" ;
NET "mcb3_dram_cas_n" LOC = "K5" ;
NET "mcb3_dram_ck" LOC = "G3" ;
NET "mcb3_dram_ck_n" LOC = "G1" ;
NET "mcb3_dram_cke" LOC = "H7" ;
NET "mcb3_dram_dm" LOC = "K3" ;
NET "mcb3_dram_dq[0]" LOC = "L2" ;
NET "mcb3_dram_dq[10]" LOC = "N2" ;
NET "mcb3_dram_dq[11]" LOC = "N1" ;
NET "mcb3_dram_dq[12]" LOC = "T2" ;
NET "mcb3_dram_dq[13]" LOC = "T1" ;
NET "mcb3_dram_dq[14]" LOC = "U2" ;
NET "mcb3_dram_dq[15]" LOC = "U1" ;
NET "mcb3_dram_dq[1]" LOC = "L1" ;
NET "mcb3_dram_dq[2]" LOC = "K2" ;
NET "mcb3_dram_dq[3]" LOC = "K1" ;
NET "mcb3_dram_dq[4]" LOC = "H2" ;
NET "mcb3_dram_dq[5]" LOC = "H1" ;
NET "mcb3_dram_dq[6]" LOC = "J3" ;
NET "mcb3_dram_dq[7]" LOC = "J1" ;
NET "mcb3_dram_dq[8]" LOC = "M3" ;
NET "mcb3_dram_dq[9]" LOC = "M1" ;
NET "mcb3_dram_dqs" LOC = "L4" ;
NET "mcb3_dram_dqs_n" LOC = "L3" ;
NET "mcb3_dram_odt" LOC = "K6" ;
NET "mcb3_dram_ras_n" LOC = "L5" ;
NET "mcb3_dram_reset_n" LOC = "E4" ;
NET "mcb3_dram_udm" LOC = "K4" ;
NET "mcb3_dram_udqs" LOC = "P2" ;
NET "mcb3_dram_udqs_n" LOC = "P1" ;
NET "mcb3_dram_we_n" LOC = "E3" ;
##################################################################################
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_rzq" LOC = "C2" ;
##################################################################################
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_zio" LOC = "L6" ;
##################################################################################
#VGA pin define
##################################################################################
#NET key1 LOC = P7 | IOSTANDARD = "LVCMOS33"; ##
#PIN "XLXI_563/mig_39_2_inst/memc3_infrastructure_inst/U_BUFG_CLK2.O"
# CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "reg_config_inst/clock_20k_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
######SD
NET SD_clk LOC = T18 ; ## CLK/SCK
NET SD_cs LOC = P18 ; ## DAT3/CS
NET SD_datain LOC = P17 ; ## CMD/DI
NET SD_dataout LOC = T17 ; ## DATA0/DO
PIN "XLXI_120/clkout4_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "XLXI_65/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "XLXI_570/bufg_insta.O" CLOCK_DEDICATED_ROUTE = FALSE;

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/UAV_CMOS.xise Normal file
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<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="300ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Verilog" xil_pn:valueState="non-default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="UAV_CMOS.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|usb_controller_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="UAV_CMOS" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-09-04T18:41:23" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="01D7C2B6D9EC47A6BA9BCC7BD46CDDB2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

278
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pro/_xmsgs/xst.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd" Line 164: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_bscan.vhd" Line 162: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="89" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_bscan.vhd" Line 115: &lt;<arg fmt="%s" index="1">bscan_spartan6</arg>&gt; remains a black-box since it has no binding entity.
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_cmd_decode.vhd" Line 67: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_cmd_decode.vhd" Line 68: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_sync.vhd" Line 55: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_ctrl_out.vhd" Line 69: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_status.vhd" Line 118: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd" Line 141: Net &lt;<arg fmt="%s" index="1">iTDI_IN</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd" Line 142: Net &lt;<arg fmt="%s" index="1">iRESET_IN</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd" Line 143: Net &lt;<arg fmt="%s" index="1">iSHIFT_IN</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd" Line 144: Net &lt;<arg fmt="%s" index="1">iUPDATE_IN</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd" Line 145: Net &lt;<arg fmt="%s" index="1">iCAPTURE_IN</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd" Line 146: Net &lt;<arg fmt="%s" index="1">iSEL_IN</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd" Line 147: Net &lt;<arg fmt="%s" index="1">iDRCK_IN</arg>&gt; does not have a driver.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">TDI_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">TDO_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">RESET_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">SHIFT_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">UPDATE_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">CAPTURE_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">SEL_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">DRCK_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">TAP_TDO_O</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\icon_pro.vhd</arg>&quot; line <arg fmt="%s" index="2">41</arg>: Output port &lt;<arg fmt="%s" index="3">TAP_TDO_OE_O</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TDI_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TDO_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SHIFT_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">UPDATE_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CAPTURE_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SEL_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DRCK_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd</arg>&quot; line <arg fmt="%s" index="2">287</arg>: Output port &lt;<arg fmt="%s" index="3">TDI_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_ICON</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd</arg>&quot; line <arg fmt="%s" index="2">287</arg>: Output port &lt;<arg fmt="%s" index="3">TDO_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_ICON</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd</arg>&quot; line <arg fmt="%s" index="2">287</arg>: Output port &lt;<arg fmt="%s" index="3">RESET_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_ICON</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd</arg>&quot; line <arg fmt="%s" index="2">287</arg>: Output port &lt;<arg fmt="%s" index="3">SHIFT_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_ICON</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd</arg>&quot; line <arg fmt="%s" index="2">287</arg>: Output port &lt;<arg fmt="%s" index="3">UPDATE_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_ICON</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd</arg>&quot; line <arg fmt="%s" index="2">287</arg>: Output port &lt;<arg fmt="%s" index="3">CAPTURE_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_ICON</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd</arg>&quot; line <arg fmt="%s" index="2">287</arg>: Output port &lt;<arg fmt="%s" index="3">SEL_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_ICON</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\chipscope_icon.vhd</arg>&quot; line <arg fmt="%s" index="2">287</arg>: Output port &lt;<arg fmt="%s" index="3">DRCK_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_ICON</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL1</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL2</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL3</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL4</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL5</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL6</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL7</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL8</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL9</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL10</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL11</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL12</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL13</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="2563" delta="new" >Inout &lt;<arg fmt="%s" index="1">CONTROL14</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">Z</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">TDI_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">TDO_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">RESET_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">SHIFT_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">UPDATE_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">CAPTURE_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">SEL_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">DRCK_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
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<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iTDI_IN</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
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<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iRESET_IN</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
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<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iSHIFT_IN</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
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<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iUPDATE_IN</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
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<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCAPTURE_IN</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
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<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_core.vhd</arg>&quot; line <arg fmt="%s" index="2">343</arg>: Output port &lt;<arg fmt="%s" index="3">COMMAND</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_CMD</arg>&gt; is unconnected or connected to loadless signal.
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</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TAP_TDI_IPAD</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TAP_TMS_IPAD</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TAP_TCK_IPAD</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_bscan.vhd</arg>&quot; line <arg fmt="%s" index="2">686</arg>: Output port &lt;<arg fmt="%s" index="3">RUNTEST</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">I_S6.ISYN.I_USE_SOFTBSCAN_EQ0.U_BS</arg>&gt; is unconnected or connected to loadless signal.
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<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_bscan.vhd</arg>&quot; line <arg fmt="%s" index="2">686</arg>: Output port &lt;<arg fmt="%s" index="3">TCK</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">I_S6.ISYN.I_USE_SOFTBSCAN_EQ0.U_BS</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\tmp\_cg\_bbx\chipscope_icon_v1_06_a\icon_bscan.vhd</arg>&quot; line <arg fmt="%s" index="2">686</arg>: Output port &lt;<arg fmt="%s" index="3">TMS</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">I_S6.ISYN.I_USE_SOFTBSCAN_EQ0.U_BS</arg>&gt; is unconnected or connected to loadless signal.
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</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">SEL_EXT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CORE_ID_SEL&lt;15:1&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="2042" delta="new" >Unit <arg fmt="%s" index="1">chipscope_icon</arg>: <arg fmt="%d" index="2">504</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>

232
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pro/coregen.cgc Normal file
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<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc7vx330t</xilinx:device>
<xilinx:deviceFamily>virtex7</xilinx:deviceFamily>
<xilinx:package>ffg1157</xilinx:package>
<xilinx:speedGrade>-3</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>VHDL</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:design>

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# Date: Sat Nov 04 05:21:37 2017
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7vx330t
SET devicefamily = virtex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1157
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = .\tmp\
# CRC: 8054ceb1

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INFO:encore:314 - Created non-GUI application for batch mode execution.
Wrote CGP file for project 'coregen'.
INFO:sim:172 - Generating IP...
Resolving generic values...
Finished resolving generic values.
Generating IP...
Gathering HDL files for icon_pro root...
Creating XST project for icon_pro...
Creating XST script file for icon_pro...
Creating XST instantiation file for icon_pro...
Running XST for icon_pro...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Generating VHDL wrapper
Not generating Verilog wrapper
Creating ISE instantiation template for icon_pro...
Skipping Verilog instantiation template for icon_pro...
Finished Generation.
Generating IP instantiation template...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating metadata file...
Generating ISE project...
XCO file found: icon_pro.xco
XMDF file found: icon_pro_xmdf.tcl
Adding
D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pr
o/tmp/_cg/icon_pro.ngc -view all -origin_type created
Checking file
"D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_p
ro/tmp/_cg/icon_pro.ngc" for project device match ...
File
"D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_p
ro/tmp/_cg/icon_pro.ngc" device information matches project device.
Adding
D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pr
o/tmp/_cg/icon_pro.ucf -view all -origin_type created
Adding
D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pr
o/tmp/_cg/icon_pro.vhd -view all -origin_type created
INFO:HDLCompiler:1061 - Parsing VHDL file
"D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ico
n_pro/tmp/_cg/icon_pro.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pr
o/tmp/_cg/icon_pro.vho -view all -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
Please set the new top explicitly by running the "project set top" command.
To re-calculate the new top automatically, set the "Auto Implementation Top"
property to true.
Top level has been set to "/icon_pro"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.

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NEWPROJECT .
SETPROJECT .
SET device=xc6slx75t
SET flowvendor=Other
SET createndf=False
SET formalverification=False
SET speedgrade=-2
SET removerpms=False
SET devicefamily=spartan6
SET asysymbol=False
SET simulationfiles=structural
SET implementationfiletype=Ngc
SET busformat=BusFormatAngleBracketNotRipped
SET designentry=VHDL
SET addpads=False
SET foundationsym=False
SET package=csg484
SET vhdlsim=True
SET verilogsim=False
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
CSET number_control_ports=1
CSET component_name=icon_pro
CSET user_scan_chain=USER1
CSET constraint_type=embedded
CSET use_unused_bscan=false
CSET use_ext_bscan=false
GENERATE

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pro/icon_pro.gise Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="icon_pro.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VHO" xil_pn:name="icon_pro.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pro/icon_pro.ucf Normal file
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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pro/icon_pro.vhd Normal file
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-------------------------------------------------------------------------------
-- Copyright (c) 2017 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : icon_pro.vhd
-- /___/ /\ Timestamp : Sat Nov 04 13:22:18 China Standard Time 2017
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY icon_pro IS
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END icon_pro;
ARCHITECTURE icon_pro_a OF icon_pro IS
BEGIN
END icon_pro_a;

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-------------------------------------------------------------------------------
-- Copyright (c) 2017 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: Xilinx CORE Generator
-- / / Filename : icon_pro.vho
-- /___/ /\ Timestamp : Sat Nov 04 13:22:18 China Standard Time 2017
-- \ \ / \
-- \___\/\___\
--
-- Design Name: ISE Instantiation template
-- Component Identifier: xilinx.com:ip:chipscope_icon:1.06.a
-------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component icon_pro
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : icon_pro
port map (
CONTROL0 => CONTROL0);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

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##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Sat Nov 04 05:21:37 2017
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx75t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=icon_pro
CSET constraint_type=embedded
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T14:12:40Z
# END Extra information
GENERATE
# CRC: b34fa12d

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="icon_pro.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="icon_pro.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="icon_pro.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx75t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|icon_pro|icon_pro_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="icon_pro.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/icon_pro" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="icon_pro" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="icon_pro_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="icon_pro_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="icon_pro_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="icon_pro_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
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<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="icon_pro" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-04T13:22:27" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7EC4F951297D47CE9DDAB75AFE1728F9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/icon_pro" xil_pn:name="icon_pro.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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# Output products list for <icon_pro>
icon_pro.gise
icon_pro.ngc
icon_pro.ucf
icon_pro.vhd
icon_pro.vho
icon_pro.xco
icon_pro.xise
icon_pro_flist.txt
icon_pro_readme.txt
icon_pro_xmdf.tcl

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The following files were generated for 'icon_pro' in directory
D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

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# The package naming convention is <core_name>_xmdf
package provide icon_pro_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::icon_pro_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::icon_pro_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name icon_pro
}
# ::icon_pro_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::icon_pro_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module icon_pro
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_icon_pro/tmp/_cg/icon_pro.vhd&quot; into library work</arg>
</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\chipscope_ila.vhd" Line 292: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_reset_ctrl.vhd" Line 88: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_match.vhd" Line 93: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_match_gandx.vhd" Line 104: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_match_gandx.vhd" Line 105: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_gandx_srl_s6.vhd" Line 102: Using initial value <arg fmt="%s" index="1">&apos;1&apos;</arg> for <arg fmt="%s" index="2">logic_1</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_gand_srl_s6.vhd" Line 64: Using initial value <arg fmt="%s" index="1">&apos;1&apos;</arg> for <arg fmt="%s" index="2">logic_1</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_gand_srl_s6_slice.vhd" Line 76: Using initial value <arg fmt="%s" index="1">&apos;1&apos;</arg> for <arg fmt="%s" index="2">logic_1</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_gand_srl_s6_slice.vhd" Line 77: Using initial value <arg fmt="%s" index="1">&apos;0&apos;</arg> for <arg fmt="%s" index="2">logic_0</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_gandx_srl_s6.vhd" Line 172: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_trigcond.vhd" Line 120: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_trigcond.vhd" Line 110: Net &lt;<arg fmt="%s" index="1">iCFG_EN_VEC[15]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_match_gand.vhd" Line 83: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_match_gand.vhd" Line 84: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="871" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_gand_srl_s6_rpm_set.vhd" Line 156: Using initial value <arg fmt="%s" index="1">&quot;111111111&quot;</arg> for <arg fmt="%s" index="2">srl_remainder</arg> since it is never assigned
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_cap_storage.vhd" Line 183: Assignment to <arg fmt="%s" index="1">logic_1</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_cap_storage.vhd" Line 184: Assignment to <arg fmt="%s" index="1">logic_0</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="89" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_bram_simple_s6_ramb9.vhd" Line 130: &lt;<arg fmt="%s" index="1">ramb8bwer</arg>&gt; remains a black-box since it has no binding entity.
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_trace_buffer.vhd" Line 201: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_core.vhd" Line 383: Net &lt;<arg fmt="%s" index="1">iCFG_EN_VEC[15]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_core.vhd" Line 384: Net &lt;<arg fmt="%s" index="1">iCFG_EN_16_0</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_core.vhd" Line 385: Net &lt;<arg fmt="%s" index="1">iCFG_EN_16_1</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\chipscope_ila.vhd" Line 279: Net &lt;<arg fmt="%s" index="1">iCONTROL_IN[17]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\chipscope_ila.vhd" Line 283: Net &lt;<arg fmt="%s" index="1">iATC_CLKIN</arg>&gt; does not have a driver.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\ila_pro_0.vhd</arg>&quot; line <arg fmt="%s" index="2">45</arg>: Output port &lt;<arg fmt="%s" index="3">TRIG_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DATA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG3</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG4</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG5</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG6</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG7</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG8</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG9</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG10</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG11</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG12</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG13</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG14</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG15</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\chipscope_ila.vhd</arg>&quot; line <arg fmt="%s" index="2">1162</arg>: Output port &lt;<arg fmt="%s" index="3">TRIG_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">I_NO_D.U_ILA</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCONTROL_IN&lt;17:15&gt;</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">TRIG_OUT</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iATC_CLKIN</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_IN&lt;2:2&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_IN&lt;10:9&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_IN&lt;17:14&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CONTROL_IN&lt;34:22&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">ATC_CLKIN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_core.vhd</arg>&quot; line <arg fmt="%s" index="2">601</arg>: Output port &lt;<arg fmt="%s" index="3">HALT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_RST</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_core.vhd</arg>&quot; line <arg fmt="%s" index="2">627</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_TSEQ_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_TRIG</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_core.vhd</arg>&quot; line <arg fmt="%s" index="2">790</arg>: Output port &lt;<arg fmt="%s" index="3">CAP_EXT_TRIGOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_G2_SQ.U_CAPCTRL</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_core.vhd</arg>&quot; line <arg fmt="%s" index="2">874</arg>: Output port &lt;<arg fmt="%s" index="3">WR_TSTAMP_OVERFLOW</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_CAPSTOR</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCFG_EN_VEC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCFG_EN_16_0</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCFG_EN_16_1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_trigger.vhd</arg>&quot; line <arg fmt="%s" index="2">254</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_TC</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG_RESET</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_match_combo.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_MU</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG_RESET</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_match_combo.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_MU</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIG_RESET</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_match_combo.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_MU</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">iCFG_EN_VEC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CAP_ENDSTATE</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TSTAMP_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_16_1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_ila_v1_05_a\ila_cap_ctrl_g2_sq.vhd</arg>&quot; line <arg fmt="%s" index="2">468</arg>: Output port &lt;<arg fmt="%s" index="3">CFG_DOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">I_SRLT_NE_1.U_WHCMPCE</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">TRIGGER</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REWIND</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFG_EN_VEC</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RESET</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WR_TSTAMP</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WR_GAP</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WR_REWIND</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RD_TSTAMP_EN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WR_RESET_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_bram_simple_s6_ramb9.vhd</arg>&quot; line <arg fmt="%s" index="2">374</arg>: Output port &lt;<arg fmt="%s" index="3">DOBDO</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_RAMB9</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\tmp\_cg\_bbx\chipscope_lib_v1_03_a\cs_bram_simple_s6_ramb9.vhd</arg>&quot; line <arg fmt="%s" index="2">374</arg>: Output port &lt;<arg fmt="%s" index="3">DOPBDOP</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U_RAMB9</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>

426
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro_0/coregen.cgc Normal file
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</spirit:design>

22
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro_0/coregen.cgp Normal file
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@ -0,0 +1,22 @@
# Date: Sun Nov 05 22:43:50 2017
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7vx330t
SET devicefamily = virtex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1157
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = .\tmp\
# CRC: 8054ceb1

61
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro_0/coregen.log Normal file
View File

@ -0,0 +1,61 @@
INFO:encore:314 - Created non-GUI application for batch mode execution.
Wrote CGP file for project 'coregen'.
INFO:sim:172 - Generating IP...
Resolving generic values...
Finished resolving generic values.
Generating IP...
Gathering HDL files for ila_pro_0 root...
Creating XST project for ila_pro_0...
Creating XST script file for ila_pro_0...
Creating XST instantiation file for ila_pro_0...
Running XST for ila_pro_0...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Generating VHDL wrapper
Not generating Verilog wrapper
Creating ISE instantiation template for ila_pro_0...
Skipping Verilog instantiation template for ila_pro_0...
Finished Generation.
Generating IP instantiation template...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating metadata file...
Generating ISE project...
XCO file found: ila_pro_0.xco
XMDF file found: ila_pro_0_xmdf.tcl
Adding
D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro
_0/tmp/_cg/ila_pro_0.ngc -view all -origin_type created
Checking file
"D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pr
o_0/tmp/_cg/ila_pro_0.ngc" for project device match ...
File
"D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pr
o_0/tmp/_cg/ila_pro_0.ngc" device information matches project device.
Adding
D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro
_0/tmp/_cg/ila_pro_0.ucf -view all -origin_type created
Adding
D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro
_0/tmp/_cg/ila_pro_0.vhd -view all -origin_type created
INFO:HDLCompiler:1061 - Parsing VHDL file
"D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila
_pro_0/tmp/_cg/ila_pro_0.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro
_0/tmp/_cg/ila_pro_0.vho -view all -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
Please set the new top explicitly by running the "project set top" command.
To re-calculate the new top automatically, set the "Auto Implementation Top"
property to true.
Top level has been set to "/ila_pro_0"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.

113
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro_0/generate_ila_pro_0.xco Normal file
View File

@ -0,0 +1,113 @@
NEWPROJECT .
SETPROJECT .
SET device=xc6slx75t
SET flowvendor=Other
SET createndf=False
SET formalverification=False
SET speedgrade=-2
SET removerpms=False
SET devicefamily=spartan6
SET asysymbol=False
SET simulationfiles=structural
SET implementationfiletype=Ngc
SET busformat=BusFormatAngleBracketNotRipped
SET designentry=VHDL
SET addpads=False
SET foundationsym=False
SET package=csg484
SET vhdlsim=True
SET verilogsim=False
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
CSET enable_trigger_output_port=false
CSET data_port_width=0
CSET match_type_9=basic
CSET match_type_8=basic
CSET match_type_16=basic
CSET match_type_7=basic
CSET match_type_15=basic
CSET exclude_from_data_storage_16=false
CSET match_type_6=basic
CSET check_BramCount=true
CSET match_type_14=basic
CSET exclude_from_data_storage_15=false
CSET match_type_5=basic
CSET match_type_13=basic
CSET exclude_from_data_storage_14=false
CSET match_type_4=basic
CSET match_type_12=basic
CSET exclude_from_data_storage_13=false
CSET match_type_3=basic_with_edges
CSET match_type_11=basic
CSET exclude_from_data_storage_12=false
CSET match_type_2=basic_with_edges
CSET match_type_10=basic
CSET exclude_from_data_storage_11=false
CSET match_type_1=basic_with_edges
CSET exclude_from_data_storage_10=false
CSET use_rpms=true
CSET component_name=ila_pro_0
CSET data_same_as_trigger=true
CSET counter_width_16=Disabled
CSET counter_width_15=Disabled
CSET counter_width_14=Disabled
CSET counter_width_13=Disabled
CSET match_units_16=1
CSET enable_storage_qualification=true
CSET counter_width_12=Disabled
CSET match_units_15=1
CSET counter_width_11=Disabled
CSET match_units_14=1
CSET counter_width_10=Disabled
CSET match_units_13=1
CSET match_units_12=1
CSET match_units_11=1
CSET match_units_10=1
CSET constraint_type=embedded
CSET number_of_trigger_ports=3
CSET match_units_9=1
CSET match_units_8=1
CSET match_units_7=1
CSET match_units_6=1
CSET match_units_5=1
CSET match_units_4=1
CSET match_units_3=1
CSET match_units_2=1
CSET match_units_1=1
CSET trigger_port_width_16=1
CSET trigger_port_width_15=1
CSET trigger_port_width_14=1
CSET trigger_port_width_13=1
CSET trigger_port_width_12=1
CSET trigger_port_width_11=1
CSET trigger_port_width_10=1
CSET exclude_from_data_storage_9=false
CSET exclude_from_data_storage_8=false
CSET exclude_from_data_storage_7=false
CSET trigger_port_width_9=1
CSET exclude_from_data_storage_6=false
CSET sample_on=Rising
CSET exclude_from_data_storage_5=false
CSET trigger_port_width_8=1
CSET trigger_port_width_7=1
CSET exclude_from_data_storage_4=false
CSET trigger_port_width_6=1
CSET max_sequence_levels=16
CSET exclude_from_data_storage_3=false
CSET trigger_port_width_5=1
CSET exclude_from_data_storage_2=false
CSET trigger_port_width_4=1
CSET exclude_from_data_storage_1=false
CSET sample_data_depth=1024
CSET trigger_port_width_3=2
CSET trigger_port_width_2=11
CSET counter_width_9=Disabled
CSET trigger_port_width_1=64
CSET counter_width_8=Disabled
CSET counter_width_7=Disabled
CSET counter_width_6=Disabled
CSET counter_width_5=Disabled
CSET counter_width_4=Disabled
CSET counter_width_3=Disabled
CSET counter_width_2=Disabled
CSET counter_width_1=Disabled
GENERATE

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#ChipScope Core Generator Project File Version 3.0
#Mon Nov 06 06:46:19 China Standard Time 2017
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SignalExport.bus<0000>.name=TRIG0
SignalExport.bus<0000>.offset=0.0
SignalExport.bus<0000>.precision=0
SignalExport.bus<0000>.radix=Bin
SignalExport.bus<0000>.scaleFactor=1.0
SignalExport.bus<0001>.channelList=64 65 66 67 68 69 70 71 72 73 74
SignalExport.bus<0001>.name=TRIG1
SignalExport.bus<0001>.offset=0.0
SignalExport.bus<0001>.precision=0
SignalExport.bus<0001>.radix=Bin
SignalExport.bus<0001>.scaleFactor=1.0
SignalExport.bus<0002>.channelList=75 76
SignalExport.bus<0002>.name=TRIG2
SignalExport.bus<0002>.offset=0.0
SignalExport.bus<0002>.precision=0
SignalExport.bus<0002>.radix=Bin
SignalExport.bus<0002>.scaleFactor=1.0
SignalExport.clockChannel=CLK
SignalExport.dataEqualsTrigger=true
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
SignalExport.triggerChannel<0000><0008>=TRIG0[8]
SignalExport.triggerChannel<0000><0009>=TRIG0[9]
SignalExport.triggerChannel<0000><0010>=TRIG0[10]
SignalExport.triggerChannel<0000><0011>=TRIG0[11]
SignalExport.triggerChannel<0000><0012>=TRIG0[12]
SignalExport.triggerChannel<0000><0013>=TRIG0[13]
SignalExport.triggerChannel<0000><0014>=TRIG0[14]
SignalExport.triggerChannel<0000><0015>=TRIG0[15]
SignalExport.triggerChannel<0000><0016>=TRIG0[16]
SignalExport.triggerChannel<0000><0017>=TRIG0[17]
SignalExport.triggerChannel<0000><0018>=TRIG0[18]
SignalExport.triggerChannel<0000><0019>=TRIG0[19]
SignalExport.triggerChannel<0000><0020>=TRIG0[20]
SignalExport.triggerChannel<0000><0021>=TRIG0[21]
SignalExport.triggerChannel<0000><0022>=TRIG0[22]
SignalExport.triggerChannel<0000><0023>=TRIG0[23]
SignalExport.triggerChannel<0000><0024>=TRIG0[24]
SignalExport.triggerChannel<0000><0025>=TRIG0[25]
SignalExport.triggerChannel<0000><0026>=TRIG0[26]
SignalExport.triggerChannel<0000><0027>=TRIG0[27]
SignalExport.triggerChannel<0000><0028>=TRIG0[28]
SignalExport.triggerChannel<0000><0029>=TRIG0[29]
SignalExport.triggerChannel<0000><0030>=TRIG0[30]
SignalExport.triggerChannel<0000><0031>=TRIG0[31]
SignalExport.triggerChannel<0000><0032>=TRIG0[32]
SignalExport.triggerChannel<0000><0033>=TRIG0[33]
SignalExport.triggerChannel<0000><0034>=TRIG0[34]
SignalExport.triggerChannel<0000><0035>=TRIG0[35]
SignalExport.triggerChannel<0000><0036>=TRIG0[36]
SignalExport.triggerChannel<0000><0037>=TRIG0[37]
SignalExport.triggerChannel<0000><0038>=TRIG0[38]
SignalExport.triggerChannel<0000><0039>=TRIG0[39]
SignalExport.triggerChannel<0000><0040>=TRIG0[40]
SignalExport.triggerChannel<0000><0041>=TRIG0[41]
SignalExport.triggerChannel<0000><0042>=TRIG0[42]
SignalExport.triggerChannel<0000><0043>=TRIG0[43]
SignalExport.triggerChannel<0000><0044>=TRIG0[44]
SignalExport.triggerChannel<0000><0045>=TRIG0[45]
SignalExport.triggerChannel<0000><0046>=TRIG0[46]
SignalExport.triggerChannel<0000><0047>=TRIG0[47]
SignalExport.triggerChannel<0000><0048>=TRIG0[48]
SignalExport.triggerChannel<0000><0049>=TRIG0[49]
SignalExport.triggerChannel<0000><0050>=TRIG0[50]
SignalExport.triggerChannel<0000><0051>=TRIG0[51]
SignalExport.triggerChannel<0000><0052>=TRIG0[52]
SignalExport.triggerChannel<0000><0053>=TRIG0[53]
SignalExport.triggerChannel<0000><0054>=TRIG0[54]
SignalExport.triggerChannel<0000><0055>=TRIG0[55]
SignalExport.triggerChannel<0000><0056>=TRIG0[56]
SignalExport.triggerChannel<0000><0057>=TRIG0[57]
SignalExport.triggerChannel<0000><0058>=TRIG0[58]
SignalExport.triggerChannel<0000><0059>=TRIG0[59]
SignalExport.triggerChannel<0000><0060>=TRIG0[60]
SignalExport.triggerChannel<0000><0061>=TRIG0[61]
SignalExport.triggerChannel<0000><0062>=TRIG0[62]
SignalExport.triggerChannel<0000><0063>=TRIG0[63]
SignalExport.triggerChannel<0001><0000>=TRIG1[0]
SignalExport.triggerChannel<0001><0001>=TRIG1[1]
SignalExport.triggerChannel<0001><0002>=TRIG1[2]
SignalExport.triggerChannel<0001><0003>=TRIG1[3]
SignalExport.triggerChannel<0001><0004>=TRIG1[4]
SignalExport.triggerChannel<0001><0005>=TRIG1[5]
SignalExport.triggerChannel<0001><0006>=TRIG1[6]
SignalExport.triggerChannel<0001><0007>=TRIG1[7]
SignalExport.triggerChannel<0001><0008>=TRIG1[8]
SignalExport.triggerChannel<0001><0009>=TRIG1[9]
SignalExport.triggerChannel<0001><0010>=TRIG1[10]
SignalExport.triggerChannel<0002><0000>=TRIG2[0]
SignalExport.triggerChannel<0002><0001>=TRIG2[1]
SignalExport.triggerPort<0000>.name=TRIG0
SignalExport.triggerPort<0001>.name=TRIG1
SignalExport.triggerPort<0002>.name=TRIG2
SignalExport.triggerPortCount=3
SignalExport.triggerPortIsData<0000>=true
SignalExport.triggerPortIsData<0001>=true
SignalExport.triggerPortIsData<0002>=true
SignalExport.triggerPortWidth<0000>=64
SignalExport.triggerPortWidth<0001>=11
SignalExport.triggerPortWidth<0002>=2
SignalExport.type=ila

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ila_pro_0.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ila_pro_0.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>

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#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_ila_pro_0 = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_ila_pro_0 = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_ila_pro_0 = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_ila_pro_0 = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
NET "TRIG1<*" S;
NET "TRIG1<*" KEEP;
NET "TRIG2<*" S;
NET "TRIG2<*" KEEP;

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-------------------------------------------------------------------------------
-- Copyright (c) 2017 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : ila_pro_0.vhd
-- /___/ /\ Timestamp : Mon Nov 06 06:46:13 China Standard Time 2017
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ila_pro_0 IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(63 downto 0);
TRIG1: in std_logic_vector(10 downto 0);
TRIG2: in std_logic_vector(1 downto 0));
END ila_pro_0;
ARCHITECTURE ila_pro_0_a OF ila_pro_0 IS
BEGIN
END ila_pro_0_a;

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-------------------------------------------------------------------------------
-- Copyright (c) 2017 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: Xilinx CORE Generator
-- / / Filename : ila_pro_0.vho
-- /___/ /\ Timestamp : Mon Nov 06 06:46:13 China Standard Time 2017
-- \ \ / \
-- \___\/\___\
--
-- Design Name: ISE Instantiation template
-- Component Identifier: xilinx.com:ip:chipscope_ila:1.05.a
-------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component ila_pro_0
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
TRIG0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
TRIG1 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
TRIG2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ila_pro_0
port map (
CONTROL => CONTROL,
CLK => CLK,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

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##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Sun Nov 05 22:43:50 2017
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx75t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=true
CSET component_name=ila_pro_0
CSET constraint_type=embedded
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=0
CSET data_same_as_trigger=true
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET example_design=false
CSET exclude_from_data_storage_1=false
CSET exclude_from_data_storage_10=false
CSET exclude_from_data_storage_11=false
CSET exclude_from_data_storage_12=false
CSET exclude_from_data_storage_13=false
CSET exclude_from_data_storage_14=false
CSET exclude_from_data_storage_15=false
CSET exclude_from_data_storage_16=false
CSET exclude_from_data_storage_2=false
CSET exclude_from_data_storage_3=false
CSET exclude_from_data_storage_4=false
CSET exclude_from_data_storage_5=false
CSET exclude_from_data_storage_6=false
CSET exclude_from_data_storage_7=false
CSET exclude_from_data_storage_8=false
CSET exclude_from_data_storage_9=false
CSET match_type_1=basic_with_edges
CSET match_type_10=basic
CSET match_type_11=basic
CSET match_type_12=basic
CSET match_type_13=basic
CSET match_type_14=basic
CSET match_type_15=basic
CSET match_type_16=basic
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic
CSET match_type_5=basic
CSET match_type_6=basic
CSET match_type_7=basic
CSET match_type_8=basic
CSET match_type_9=basic
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=16
CSET number_of_trigger_ports=3
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=64
CSET trigger_port_width_10=1
CSET trigger_port_width_11=1
CSET trigger_port_width_12=1
CSET trigger_port_width_13=1
CSET trigger_port_width_14=1
CSET trigger_port_width_15=1
CSET trigger_port_width_16=1
CSET trigger_port_width_2=11
CSET trigger_port_width_3=2
CSET trigger_port_width_4=1
CSET trigger_port_width_5=1
CSET trigger_port_width_6=1
CSET trigger_port_width_7=1
CSET trigger_port_width_8=1
CSET trigger_port_width_9=1
CSET use_rpms=true
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T14:13:15Z
# END Extra information
GENERATE
# CRC: dca10ce6

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="ila_pro_0.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="ila_pro_0.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ila_pro_0.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx75t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ila_pro_0|ila_pro_0_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="ila_pro_0.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ila_pro_0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="ila_pro_0" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ila_pro_0_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="ila_pro_0_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ila_pro_0_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ila_pro_0_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="ila_pro_0" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-06T06:46:21" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7368DEA803D34509896C32531734D4F1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/ila_pro_0" xil_pn:name="ila_pro_0.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro_0/ila_pro_0_flist.txt Normal file
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# Output products list for <ila_pro_0>
ila_pro_0.cdc
ila_pro_0.gise
ila_pro_0.ngc
ila_pro_0.ucf
ila_pro_0.vhd
ila_pro_0.vho
ila_pro_0.xco
ila_pro_0.xise
ila_pro_0_flist.txt
ila_pro_0_readme.txt
ila_pro_0_xmdf.tcl

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The following files were generated for 'ila_pro_0' in directory
D:\03_FPGA_Project\01_UAV_CMOS\02_FPGA\UAV_CMOS_2Degree\UAV_CMOS\_ngo\cs_ila_pro_0\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* ila_pro_0.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* ila_pro_0.cdc
* ila_pro_0.ngc
* ila_pro_0.ucf
* ila_pro_0.vhd
* ila_pro_0.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* ila_pro_0.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* ila_pro_0_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* ila_pro_0.gise
* ila_pro_0.xise
Deliver Readme:
Readme file for the IP.
* ila_pro_0_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* ila_pro_0_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

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# The package naming convention is <core_name>_xmdf
package provide ila_pro_0_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::ila_pro_0_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::ila_pro_0_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name ila_pro_0
}
# ::ila_pro_0_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::ila_pro_0_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.cdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ila_pro_0
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS_2Degree/UAV_CMOS/_ngo/cs_ila_pro_0/tmp/_cg/ila_pro_0.vhd&quot; into library work</arg>
</msg>
</messages>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_ngo/main_cs_signalbrowser.ver Normal file
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ISE Version 14.7.0

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G:\gitDoc\fpga\UAV_CMOS_2Degree_20171106\UAV_CMOS_2Degree\UAV_CMOS\main_cs.ngc 1510024438
OK

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Bitgen" num="341" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, requires a special bit stream format. For more information, please reference Xilinx Answer Record 39999.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">icon_control0&lt;13&gt;</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="info" file="PhysDesignRules" num="1861" delta="new" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">XLXI_570/DCM_SP_inst</arg>, consult the device Data Sheet.
</msg>
<msg type="warning" file="PhysDesignRules" num="2410" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N40</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">229</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N41,
N42,
N43,
N44,
N45</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">cmos_monitor&lt;1&gt;</arg> connected to top level port <arg fmt="%s" index="2">cmos_monitor&lt;1&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">cmos_monitor&lt;0&gt;</arg> connected to top level port <arg fmt="%s" index="2">cmos_monitor&lt;0&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">cmos_triger1</arg> connected to top level port <arg fmt="%s" index="2">cmos_triger1</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">cmos_triger2</arg> connected to top level port <arg fmt="%s" index="2">cmos_triger2</arg> has been removed.
</msg>
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="warning" file="Pack" num="2549" delta="old" >The register &quot;<arg fmt="%s" index="1">XLXI_30/direction_flag</arg>&quot; has the property IOB=TRUE, but was not packed into the OLOGIC component. <arg fmt="%z" index="2">The output signal for register symbol XLXI_30/direction_flag requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.</arg>
</msg>
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="warning" file="Pack" num="1653" delta="old" >At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE, consult the Xilinx Command Line Tools User Guide &quot;TRACE&quot; chapter.
</msg>
<msg type="info" file="Timing" num="3284" delta="old" >This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">99</arg> IOs, <arg fmt="%d" index="2">98</arg> are locked and <arg fmt="%d" index="3">1</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg>
<msg type="warning" file="Place" num="1206" delta="old" >This design contains a global buffer instance, &lt;<arg fmt="%s" index="1">XLXI_120/clkout2_buf</arg>&gt;, driving the net, &lt;<arg fmt="%s" index="2">cmos_pll_OBUF</arg>&gt;, that is driving the following (first <arg fmt="%d" index="3">30</arg>) non-clock load pins off chip.
<arg fmt="%s" index="4">&lt; PIN: cmos_pll.O; &gt;
</arg>This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution: instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to .C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">XLXI_120/clkout2_buf</arg>.<arg fmt="%s" index="6">O</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
</msg>
<msg type="warning" file="Place" num="1206" delta="old" >This design contains a global buffer instance, &lt;<arg fmt="%s" index="1">XLXI_570/bufg_insta</arg>&gt;, driving the net, &lt;<arg fmt="%s" index="2">SD_clk_OBUF</arg>&gt;, that is driving the following (first <arg fmt="%d" index="3">30</arg>) non-clock load pins off chip.
<arg fmt="%s" index="4">&lt; PIN: SD_clk.O; &gt;
</arg>This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution: instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to .C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">XLXI_570/bufg_insta</arg>.<arg fmt="%s" index="6">O</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
</msg>
<msg type="warning" file="Place" num="1137" delta="old" >This design is not guaranteed to be routable! This design contains a global buffer instance, &lt;<arg fmt="%s" index="1">XLXI_120/clkout2_buf</arg>&gt;, driving the net, &lt;<arg fmt="%s" index="2">cmos_pll_OBUF</arg>&gt;, that is driving the following (first <arg fmt="%d" index="3">30</arg>) non-clock load pins.
<arg fmt="%s" index="4">&lt; PIN: cmos_pll.O; &gt;
</arg>This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">XLXI_120/clkout2_buf</arg>.<arg fmt="%s" index="6">O</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
</msg>
<msg type="warning" file="Place" num="1137" delta="old" >This design is not guaranteed to be routable! This design contains a global buffer instance, &lt;<arg fmt="%s" index="1">XLXI_120/clkout4_buf</arg>&gt;, driving the net, &lt;<arg fmt="%s" index="2">clk_25m</arg>&gt;, that is driving the following (first <arg fmt="%d" index="3">30</arg>) non-clock load pins.
<arg fmt="%s" index="4">&lt; PIN: XLXI_570/bufg_instc.I0; &gt;
</arg>This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">XLXI_120/clkout4_buf</arg>.<arg fmt="%s" index="6">O</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
</msg>
<msg type="warning" file="Place" num="1137" delta="old" >This design is not guaranteed to be routable! This design contains a global buffer instance, &lt;<arg fmt="%s" index="1">XLXI_570/bufg_insta</arg>&gt;, driving the net, &lt;<arg fmt="%s" index="2">SD_clk_OBUF</arg>&gt;, that is driving the following (first <arg fmt="%d" index="3">30</arg>) non-clock load pins.
<arg fmt="%s" index="4">&lt; PIN: SD_clk.O; &gt;
</arg>This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">XLXI_570/bufg_insta</arg>.<arg fmt="%s" index="6">O</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
</msg>
<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">icon_control0&lt;13&gt;</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="info" file="PhysDesignRules" num="1861" delta="new" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">XLXI_570/DCM_SP_inst</arg>, consult the device Data Sheet.
</msg>
<msg type="warning" file="PhysDesignRules" num="2410" delta="new" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">CMOS_CLK</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_CMOS_CLK</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">u_pll_adv</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT3</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD &quot;XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in&quot; TS_CMOS_CLK * 1.5625 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">CMOS_CLK</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_CMOS_CLK</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">u_pll_adv</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT1</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_clk_2x_180 = PERIOD &quot;XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_clk_2x_180&quot; TS_CMOS_CLK * 12.5 PHASE 0.666666667 ns HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">CMOS_CLK</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_CMOS_CLK</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">u_pll_adv</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT5</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in = PERIOD &quot;XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in&quot; TS_CMOS_CLK * 0.5 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">CMOS_CLK</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_CMOS_CLK</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">u_pll_adv</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT0</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_clk_2x_0 = PERIOD &quot;XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_clk_2x_0&quot; TS_CMOS_CLK * 12.5 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">CMOS_CLK</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_CMOS_CLK</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">u_pll_adv</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT2</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_clk0_bufg_in = PERIOD &quot;XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_clk0_bufg_in&quot; TS_CMOS_CLK * 1.5625 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">USB_SCLK</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_USB_SCLK</arg>&apos;, was traced into <arg fmt="%s" index="4">DCM_SP</arg> instance <arg fmt="%s" index="5">dcm_sp_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">DCM_SP</arg> output(s):
<arg fmt="%s" index="7">CLK0</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_65_clk0 = PERIOD &quot;XLXI_65_clk0&quot; TS_USB_SCLK PHASE 1.278409091 ns HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">LVDS_CLK_N</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_LVDS_CLK_N</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT1</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_559_clkout1 = PERIOD &quot;XLXI_559_clkout1&quot; TS_LVDS_CLK_N PHASE 1 ns HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">LVDS_CLK_N</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_LVDS_CLK_N</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT0</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_559_clkout0 = PERIOD &quot;XLXI_559_clkout0&quot; TS_LVDS_CLK_N PHASE -1 ns HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT3</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_120_clkout3 = PERIOD &quot;XLXI_120_clkout3&quot; TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT1</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_120_clkout1 = PERIOD &quot;XLXI_120_clkout1&quot; TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in * 1.6 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT0</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_120_clkout0 = PERIOD &quot;XLXI_120_clkout0&quot; TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in * 0.125 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="new" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">PLL_ADV</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT2</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_clk_100m = PERIOD &quot;clk_100m&quot; TS_XLXI_596_mig_39_2_inst_memc3_infrastructure_inst_vga_clk_bufg_in * 4 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">XLXI_120_clkout3</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_XLXI_120_clkout3</arg>&apos;, was traced into <arg fmt="%s" index="4">DCM_SP</arg> instance <arg fmt="%s" index="5">DCM_SP_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">DCM_SP</arg> output(s):
<arg fmt="%s" index="7">CLKFX</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_XLXI_570_CLKFX = PERIOD &quot;XLXI_570_CLKFX&quot; TS_XLXI_120_clkout3 HIGH 50%&gt;</arg>
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_15 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_15</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_15&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(81)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_14 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_14</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_14&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(80)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_13 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_13</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_13&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(79)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_12 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_12</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_12&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(78)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_11 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_11</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_11&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(77)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_10 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_10</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_10&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(76)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_9 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_9</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_9&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(75)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_8 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_8</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_8&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(74)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_7 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_7</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_7&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(73)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_6 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_6</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_6&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(72)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_5 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_5</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_5&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(71)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_4 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_4</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_4&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(70)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_3 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_3</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_3&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(69)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_2 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_2</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_2&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(68)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_1 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_1</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_1&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(67)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_in_buf_0 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_in_buf_0</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_in_buf_0&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(66)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_15 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_15</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_15&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(98)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_14 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_14</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_14&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(97)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_13 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_13</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_13&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(96)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_12 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_12</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_12&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(95)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_11 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_11</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_11&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(94)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_10 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_10</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_10&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(93)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_9 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_9</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_9&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(92)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_8 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_8</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_8&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(91)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_7 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_7</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_7&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(90)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_6 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_6</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_6&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(89)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_5 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_5</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_5&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(88)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_4 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_4</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_4&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(87)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_3 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_3</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_3&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(86)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_2 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_2</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_2&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(85)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_1 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_1</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_1&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(84)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1012" delta="old" >The constraint <arg fmt="%s" index="1">&lt;INST /main/EXPANDED/main/XLXI_30/USB_Data_out_buf_0 IOB = true&gt;</arg> is overridden on the design object <arg fmt="%s" index="2">XLXI_30/USB_Data_out_buf_0</arg> by the constraint <arg fmt="%s" index="3">&lt;INST &quot;XLXI_30/USB_Data_out_buf_0&quot; IOB =TRUE;&gt; [UAV_CMOS.ucf(83)]</arg>.
</msg>
<msg type="warning" file="NgdBuild" num="1440" delta="old" >User specified non-default attribute value (<arg fmt="%s" index="1">20</arg>) was detected for the <arg fmt="%s" index="2">CLKIN1_PERIOD</arg> attribute on <arg fmt="%s" index="3">PLL</arg> &quot;<arg fmt="%s" index="4">u_pll_adv</arg>&quot;. This does not match the PERIOD constraint value (<arg fmt="%s" index="5">60 MHz.</arg>). The uncertainty calculation will use the PERIOD constraint value. This could result in incorrect uncertainty calculated for <arg fmt="%s" index="6">PLL</arg> output clocks.
</msg>
<msg type="warning" file="NgdBuild" num="1212" delta="old" >User specified non-default attribute value (<arg fmt="%s" index="1">20.000000</arg>) was detected for the <arg fmt="%s" index="2">CLKIN_PERIOD</arg> attribute on <arg fmt="%s" index="3">DCM</arg> &quot;<arg fmt="%s" index="4">DCM_SP_inst</arg>&quot;. This does not match the PERIOD constraint value (<arg fmt="%s" index="5">30 MHz.</arg>). The uncertainty calculation will use the non-default attribute value. This could result in incorrect uncertainty calculated for <arg fmt="%s" index="6">DCM</arg> output clocks.
</msg>
<msg type="warning" file="NgdBuild" num="1212" delta="old" >User specified non-default attribute value (<arg fmt="%s" index="1">20.833000</arg>) was detected for the <arg fmt="%s" index="2">CLKIN_PERIOD</arg> attribute on <arg fmt="%s" index="3">DCM</arg> &quot;<arg fmt="%s" index="4">dcm_sp_inst</arg>&quot;. This does not match the PERIOD constraint value (<arg fmt="%s" index="5">55 MHz.</arg>). The uncertainty calculation will use the non-default attribute value. This could result in incorrect uncertainty calculated for <arg fmt="%s" index="6">DCM</arg> output clocks.
</msg>
<msg type="warning" file="NgdBuild" num="1440" delta="old" >User specified non-default attribute value (<arg fmt="%s" index="1">40</arg>) was detected for the <arg fmt="%s" index="2">CLKIN1_PERIOD</arg> attribute on <arg fmt="%s" index="3">PLL</arg> &quot;<arg fmt="%s" index="4">PLL_ADV</arg>&quot;. This does not match the PERIOD constraint value (<arg fmt="%s" index="5">30 MHz.</arg>). The uncertainty calculation will use the PERIOD constraint value. This could result in incorrect uncertainty calculated for <arg fmt="%s" index="6">PLL</arg> output clocks.
</msg>
<msg type="warning" file="NgdBuild" num="1440" delta="old" >User specified non-default attribute value (<arg fmt="%s" index="1">5</arg>) was detected for the <arg fmt="%s" index="2">CLKIN1_PERIOD</arg> attribute on <arg fmt="%s" index="3">PLL</arg> &quot;<arg fmt="%s" index="4">PLL_ADV</arg>&quot;. This does not match the PERIOD constraint value (<arg fmt="%s" index="5">4 ns.</arg>). The uncertainty calculation will use the PERIOD constraint value. This could result in incorrect uncertainty calculated for <arg fmt="%s" index="6">PLL</arg> output clocks.
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">cmos_triger1_OBUF</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">cmos_triger2_OBUF</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N40</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N41</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N42</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N43</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N44</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N45</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N46</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N47</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N48</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N49</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N50</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N51</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N52</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N53</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N54</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N55</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N56</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N57</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N58</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N59</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N60</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N61</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N62</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N63</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N64</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N65</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N66</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N67</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N68</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N69</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N70</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N71</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N72</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N73</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N74</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N75</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N76</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N77</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="478" delta="old" >clock net <arg fmt="%s" index="1">XLXI_596/camera_clk</arg> with clock driver <arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/memc3_infrastructure_inst/U_BUFG_CLK2</arg> drives no clock pins
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/c3_p0_wr_underrun</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p0_cmd_byte_addr&lt;29&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p0_cmd_byte_addr&lt;28&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p0_cmd_byte_addr&lt;27&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p1_cmd_byte_addr&lt;29&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p1_cmd_byte_addr&lt;28&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p1_cmd_byte_addr&lt;27&gt;</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p0_wr_error</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p0_rd_overflow</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p0_rd_error</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_596/mig_39_2_inst/c3_p1_wr_underrun</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_348/LVDS_Channel1</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_348/LVDS_Channel2</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_348/LVDS_Channel3</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_127/rst</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">XLXI_112/rst</arg>&apos; has no driver
</msg>
</messages>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_xmsgs/par.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Par" num="450" delta="old" >At least one timing constraint is impossible to meet because component switching limit violations have been detected for a constrained component. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to evaluate the component switching limit violations in more detail. Evaluate the datasheet for alternative configurations for the component that could allow the frequencies requested in the constraint. Otherwise, the timing constraint covering this component might need to be modified to satisfy the component switching limits specified in the datasheet.
</msg>
<msg type="info" file="Timing" num="3284" delta="old" >This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">USB_FlagB_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">USB_FlagD_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data&lt;7&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data&lt;6&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data&lt;5&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data&lt;4&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data&lt;3&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data&lt;2&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data&lt;1&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data&lt;0&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_data_valid</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_cmd_ready_in</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/uo_cal_start</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">XLXI_596/mig_39_2_inst/memc3_infrastructure_inst/clk0</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="468" delta="old" >Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select &quot;Post-Place &amp;
Route Static Timing Report&quot;). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -&gt; Design Goals &amp; Strategies) to ensure the best options are set in the tools for timing closure.
</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">14</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">14</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
</messages>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_xmsgs/pn_parser.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
</messages>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_xmsgs/trce.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>

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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_xmsgs/xdl.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="XDL" num="213" delta="new" >The resulting xdl output will not have LUT equation strings or RAM INIT strings.
</msg>
</messages>

4754
使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/_xmsgs/xst.xmsgs Normal file
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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/cmos_controller.cpj Normal file
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使用FPGA、DDR3和SDHC卡的高速地表图像采集及存储系统/projects/UAV_CMOS_2Degree_20171106/UAV_CMOS_2Degree/UAV_CMOS/cmos_interface.cmd_log Normal file
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vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/cmos_interface.v -lang verilog -prj UAV_CMOS -o cmos_interface.spl -module cmos_interface -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l cmos_interface.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/cmos_interface.sym
vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/cmos_interface.v -lang verilog -prj UAV_CMOS -o cmos_interface.spl -module cmos_interface -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l cmos_interface.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/cmos_interface.sym
vhdtdtfi -lib work D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/cmos_interface.v -lang verilog -prj UAV_CMOS -o cmos_interface.spl -module cmos_interface -template D:/01_Installed_SW/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family spartan6l cmos_interface.spl D:/03_FPGA_Project/01_UAV_CMOS/02_FPGA/UAV_CMOS/UAV_CMOS/cmos_interface.sym

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