myhdl/.hgignore

syntax: glob
.project
.pydevproject
CHANGELOG.txt
MANIFEST
modelsim.ini
transcript
*~
*.pyc
*.swp
*.v
*.vhd
*_ghdl
*.o
*.so
*.log
*.cf
*.vpi
*.orig
*.vcd
*.0
*.bak
*.wlf
*.rej
*.out
doc/build
build/
dist/
old_conversion/
work/
work_vlog/
work_vcom/
*egg-info/
ignore patterns 2008-05-28 14:28:29 +02:00			`syntax: glob`
Support for conversion of ternary operator. They are converted to ternary equivalents in the target HDL. If possible, they are converted to single line assigns. Within a process, this will only work with VHDL-2008. 2010-07-01 19:13:42 +02:00			`.project`
			`.pydevproject`
prepare for development release 2008-08-21 15:29:10 +02:00			`CHANGELOG.txt`
			`MANIFEST`
vsim intro 2010-09-11 23:15:09 +02:00			`modelsim.ini`
			`transcript`
ignore patterns 2008-05-28 14:28:29 +02:00			`*~`
			`*.pyc`
print with more than one argument does not raise an error anymore but creates a warning. 2008-07-22 14:14:30 +02:00			`*.swp`
ignore patterns 2008-06-16 20:38:11 +02:00			`*.v`
			`*.vhd`
			`*_ghdl`
			`*.o`
			`*.so`
			`*.log`
			`*.cf`
			`*.vpi`
			`*.orig`
prepare for development release 2008-08-21 15:29:10 +02:00			`*.vcd`
			`*.0`
Support for conversion of ternary operator. They are converted to ternary equivalents in the target HDL. If possible, they are converted to single line assigns. Within a process, this will only work with VHDL-2008. 2010-07-01 19:13:42 +02:00			`*.bak`
vsim intro 2010-09-11 23:15:09 +02:00			`*.wlf`
break up the modeling chapter in three Mark high level clearly as separate from synthesis --HG-- branch : 0.8-dev 2012-05-06 09:59:31 +02:00			`*.rej`
			`*.out`
ignore patterns 2008-05-28 14:28:29 +02:00			`doc/build`
Avoid Array Error 2008-07-22 09:48:45 +02:00			`build/`
prepare for development release 2008-08-21 15:29:10 +02:00			`dist/`
Support for conversion of ternary operator. They are converted to ternary equivalents in the target HDL. If possible, they are converted to single line assigns. Within a process, this will only work with VHDL-2008. 2010-07-01 19:13:42 +02:00			`old_conversion/`
introduced vsim as unit test simulator (both with vlog and vcom) 2010-09-11 23:08:51 +02:00			`work/`
			`work_vlog/`
vsim intro 2010-09-11 23:15:09 +02:00			`work_vcom/`
Added *egg-info/ --HG-- branch : mep107 2013-07-06 17:54:01 -04:00			`*egg-info/`