2015-02-01 18:00:29 -05:00
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from __future__ import absolute_import
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2011-05-18 10:36:04 +02:00
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from myhdl import *
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from timer import timer_sig, timer_var
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def test_timer(timer):
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MAXVAL = 1234
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clock = Signal(bool())
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reset = Signal(bool())
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flag = Signal(bool())
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dut = timer(flag, clock, reset, MAXVAL)
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@instance
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def clkgen():
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clock.next = 0
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reset.next = 0
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yield delay(10)
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reset.next = 1
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yield delay(10)
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reset.next = 0
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yield delay(10)
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2011-05-20 09:14:06 +02:00
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for i in range(2**25):
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2011-05-18 10:36:04 +02:00
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clock.next = not clock
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yield delay(10)
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@instance
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def monitor():
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count = intbv(0, min=0, max=MAXVAL+1)
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seen = False
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while True:
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yield clock.posedge
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if seen:
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if flag:
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assert count == MAXVAL
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else:
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count += 1
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if flag:
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seen = True
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count[:] = 0
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return dut, clkgen, monitor
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if __name__ == '__main__':
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sim = Simulation(test_timer(timer_var))
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sim.run()
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2014-04-11 15:02:50 +02:00
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