2003-02-04 23:02:56 +00:00
|
|
|
from __future__ import generators
|
2004-01-28 09:55:45 +00:00
|
|
|
from myhdl import Signal, delay, Simulation, intbv, bin, traceSignals
|
2003-02-04 23:02:56 +00:00
|
|
|
|
2003-02-17 12:26:22 +00:00
|
|
|
def bin2gray(B, G, width):
|
2003-02-05 22:07:33 +00:00
|
|
|
""" Gray encoder.
|
|
|
|
|
|
|
|
B -- input intbv signal, binary encoded
|
|
|
|
G -- output intbv signal, gray encoded
|
2003-02-17 12:26:22 +00:00
|
|
|
width -- bit width
|
2003-02-05 22:07:33 +00:00
|
|
|
"""
|
2003-02-04 23:02:56 +00:00
|
|
|
while 1:
|
|
|
|
yield B
|
|
|
|
for i in range(width):
|
2003-02-15 14:54:40 +00:00
|
|
|
G.next[i] = B[i+1] ^ B[i]
|
2003-02-04 23:02:56 +00:00
|
|
|
|
2003-02-06 22:37:20 +00:00
|
|
|
def testBench(width):
|
2003-02-04 23:02:56 +00:00
|
|
|
|
|
|
|
B = Signal(intbv(0))
|
|
|
|
G = Signal(intbv(0))
|
|
|
|
|
2004-01-28 09:55:45 +00:00
|
|
|
dut = traceSignals(bin2gray, B, G, width)
|
2003-02-04 23:02:56 +00:00
|
|
|
|
|
|
|
def stimulus():
|
|
|
|
for i in range(2**width):
|
|
|
|
B.next = intbv(i)
|
|
|
|
yield delay(10)
|
2003-02-15 14:54:40 +00:00
|
|
|
print "B: " + bin(B, width) + "| G: " + bin(G, width)
|
2003-02-04 23:02:56 +00:00
|
|
|
|
|
|
|
return (dut, stimulus())
|
|
|
|
|
2003-06-30 14:24:23 +00:00
|
|
|
def main():
|
2003-02-06 22:37:20 +00:00
|
|
|
Simulation(testBench(width=3)).run()
|
2003-02-04 23:02:56 +00:00
|
|
|
|
|
|
|
|
2003-06-30 14:24:23 +00:00
|
|
|
if __name__ == '__main__':
|
|
|
|
main()
|
|
|
|
|
|
|
|
|