myhdl/example/manual/rom.v

// File: rom.v
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008

`timescale 1ns/10ps

module rom (
    dout,
    addr
);

output [7:0] dout;
reg [7:0] dout;
input [3:0] addr;




always @(addr) begin: ROM_READ
    // synthesis parallel_case full_case
    case (addr)
        0: dout <= 17;
        1: dout <= 134;
        2: dout <= 52;
        default: dout <= 9;
    endcase
end

endmodule