2005-12-27 14:45:38 +00:00
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MyHDL co-simulation relies on Unix-style interprocess communication.
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To run co-simulation on Windows, compile and use all tools involved
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(including Python itself) on a Unix-like environment for Windows, such
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as cygwin.
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2008-07-21 23:21:18 +02:00
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For co-simulation with cver, the following is required:
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* a working cver installation
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* a 'myhdl_vpi.so' file, generated from 'myhdl_vpi.c'
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2004-03-02 11:11:31 +00:00
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2008-07-21 23:21:18 +02:00
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For Linux, a makefile 'makefile.lnx' is provided to generate 'myhdl_vpi.so'.
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However, you will have to edit the makefile to point to the correct
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pli include files for cver. See the makefile for instructions.
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2004-03-02 11:11:31 +00:00
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To test whether it works, go to the 'test' subdirectory and run the
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tests with 'python test_all.py'.
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2004-03-19 12:15:36 +00:00
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For co-simulation with MyHDL, 'cver' should be run with the 'myhdl_vpi.so'
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2004-03-02 11:11:31 +00:00
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PLI module, using the '+loadvpi' option, and with the 'vpi_compat_bootstrap'
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routine as the bootstrap routine. The Verilog code should contain the
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appropriate calls to the '$to_myhdl' and 'from_myhdl' tasks.
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2004-03-19 12:15:36 +00:00
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The 'myhdl_vpi.c' module was developed and verified with cver version
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2004-03-02 11:11:31 +00:00
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GPLCVER_1.10f on Linux.
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