2016-05-11 12:08:15 +02:00
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import random
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2016-05-23 15:56:00 +02:00
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from myhdl import block, always, instance, Signal, \
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ResetSignal, modbv, delay, StopSimulation
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2016-05-11 12:08:15 +02:00
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from inc import inc
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random.seed(1)
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randrange = random.randrange
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ACTIVE_LOW, INACTIVE_HIGH = 0, 1
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@block
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def testbench():
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m = 3
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count = Signal(modbv(0)[m:])
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enable = Signal(bool(0))
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clock = Signal(bool(0))
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2018-08-14 14:46:32 -07:00
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reset = ResetSignal(0, active=0, isasync=True)
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2016-05-11 12:08:15 +02:00
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inc_1 = inc(count, enable, clock, reset)
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HALF_PERIOD = delay(10)
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@always(HALF_PERIOD)
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def clockGen():
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clock.next = not clock
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@instance
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def stimulus():
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reset.next = ACTIVE_LOW
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yield clock.negedge
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reset.next = INACTIVE_HIGH
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for i in range(16):
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enable.next = min(1, randrange(3))
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yield clock.negedge
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raise StopSimulation()
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@instance
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def monitor():
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print("enable count")
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yield reset.posedge
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while 1:
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yield clock.posedge
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yield delay(1)
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print(" %s %s" % (int(enable), count))
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return clockGen, stimulus, inc_1, monitor
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tb = testbench()
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tb.run_sim()
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