2015-03-24 03:49:56 -04:00
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""" myhdl's distribution and installation script. """
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2003-01-30 12:19:52 +00:00
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2015-03-24 03:57:27 -04:00
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import ast
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2015-03-29 10:46:15 -04:00
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import fnmatch
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2015-03-24 03:57:27 -04:00
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import re
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2015-03-29 10:46:15 -04:00
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import os
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2003-01-30 17:19:02 +00:00
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import sys
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2015-03-29 10:46:15 -04:00
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from collections import defaultdict
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Update makeflow (#396)
* Clean up verify convert warnings
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Fixed all tests to handle the analyze/verify deprecation
* Fixed to catch the correct error, List of signals as a port is not supported
* Add a way to search for and add myhdl.vpi
* Add explict test to check for deprecation case
* Change warning from UserWarning (which is the default) to DeprecationWarning
* Change test operation from script to makefile
* No longer use travis
* Add some ANSI colored logging
* Fixed test to look for DeprecationWarning
* Add lining step
* Add linting step
* Add linting step
* Remove matrix step
* Add work/ to clean list
* Hide echo commands in window
* The word test is reserved in pytest only for tests, doen't use it for any thing else, like blocks
* Add myhdl.vpi to clean
* Mark these tests as xfail, for now,
* Fix and unmark xfail 2 tests
* Add black support
* Remove python2 only testing
* Need to relook at this test, it performs differently for verilog and vhdl
* Add RTL files to the list
* Need to relook at this test, it performs differently for verilog and vhdl
* Upgrade to DeprecationWarnings
* Initial checkin with passing flow for new convert VHDL/Verilog, there are a few xfail tests that need to be debugged
* Add more examples for the Deprecation cases, toVHDL and toVerilog
* Fix deprecations catching
* Fix pytest to use pytest.ini
* Add pypi release steps
* Fix intbv error
* Fix indent
* Update to do a release
* Add checkout to step
* Update Python versions
* Add dependancy on tag on push
2022-12-17 12:21:08 +00:00
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if sys.version_info < (3, 7):
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raise RuntimeError("Python version 3.7+ required.")
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2006-03-08 16:04:18 +00:00
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2003-01-23 23:21:31 +00:00
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2015-03-24 03:49:56 -04:00
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# Prefer setuptools over distutils
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2003-01-30 17:19:02 +00:00
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try:
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2015-03-24 03:49:56 -04:00
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from setuptools import setup
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except ImportError:
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from distutils.core import setup
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2015-03-24 03:57:27 -04:00
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_version_re = re.compile(r'__version__\s+=\s+(.*)')
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with open('myhdl/__init__.py', 'rb') as f:
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version = str(ast.literal_eval(_version_re.search(
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f.read().decode('utf-8')).group(1)))
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2015-03-29 10:46:15 -04:00
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data_root = 'share/myhdl'
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cosim_data = defaultdict(list)
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for base, dir, files in os.walk('cosimulation'):
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for pat in ('*.c', 'Makefile*', '*.py', '*.v', '*.txt'):
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good = fnmatch.filter(files, pat)
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if good:
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2015-03-29 11:23:22 -04:00
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cosim_data[base].extend(os.path.join(base, f) for f in good)
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2015-03-24 03:57:27 -04:00
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2022-12-18 19:30:27 +00:00
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def read(fname):
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return open(os.path.join(os.path.dirname(__file__), fname)).read()
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2015-03-24 03:49:56 -04:00
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setup(
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name="myhdl",
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2015-03-24 03:57:27 -04:00
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version=version,
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2015-03-24 03:49:56 -04:00
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description="Python as a Hardware Description Language",
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2022-12-18 19:30:27 +00:00
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long_description=read('README.md'),
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long_description_content_type='text/markdown',
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2015-03-24 03:49:56 -04:00
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author="Jan Decaluwe",
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author_email="jan@jandecaluwe.com",
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url="http://www.myhdl.org",
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packages=['myhdl', 'myhdl.conversion'],
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2015-03-29 10:46:15 -04:00
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data_files=[(os.path.join(data_root, k), v) for k, v in cosim_data.items()],
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2015-03-24 03:49:56 -04:00
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license="LGPL",
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platforms='any',
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keywords="HDL ASIC FPGA hardware design",
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Update makeflow (#396)
* Clean up verify convert warnings
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Fixed all tests to handle the analyze/verify deprecation
* Fixed to catch the correct error, List of signals as a port is not supported
* Add a way to search for and add myhdl.vpi
* Add explict test to check for deprecation case
* Change warning from UserWarning (which is the default) to DeprecationWarning
* Change test operation from script to makefile
* No longer use travis
* Add some ANSI colored logging
* Fixed test to look for DeprecationWarning
* Add lining step
* Add linting step
* Add linting step
* Remove matrix step
* Add work/ to clean list
* Hide echo commands in window
* The word test is reserved in pytest only for tests, doen't use it for any thing else, like blocks
* Add myhdl.vpi to clean
* Mark these tests as xfail, for now,
* Fix and unmark xfail 2 tests
* Add black support
* Remove python2 only testing
* Need to relook at this test, it performs differently for verilog and vhdl
* Add RTL files to the list
* Need to relook at this test, it performs differently for verilog and vhdl
* Upgrade to DeprecationWarnings
* Initial checkin with passing flow for new convert VHDL/Verilog, there are a few xfail tests that need to be debugged
* Add more examples for the Deprecation cases, toVHDL and toVerilog
* Fix deprecations catching
* Fix pytest to use pytest.ini
* Add pypi release steps
* Fix intbv error
* Fix indent
* Update to do a release
* Add checkout to step
* Update Python versions
* Add dependancy on tag on push
2022-12-17 12:21:08 +00:00
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python_requires='>=3.7',
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2015-03-24 03:49:56 -04:00
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classifiers=[
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'Development Status :: 5 - Production/Stable',
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'Intended Audience :: Developers',
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'Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)',
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'License :: OSI Approved :: GNU Lesser General Public License v2 (LGPLv2)',
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'Operating System :: OS Independent',
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'Programming Language :: Python',
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'Programming Language :: Python :: 3',
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2019-03-12 17:51:12 +02:00
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'Programming Language :: Python :: 3.7',
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Update makeflow (#396)
* Clean up verify convert warnings
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Fixed all tests to handle the analyze/verify deprecation
* Fixed to catch the correct error, List of signals as a port is not supported
* Add a way to search for and add myhdl.vpi
* Add explict test to check for deprecation case
* Change warning from UserWarning (which is the default) to DeprecationWarning
* Change test operation from script to makefile
* No longer use travis
* Add some ANSI colored logging
* Fixed test to look for DeprecationWarning
* Add lining step
* Add linting step
* Add linting step
* Remove matrix step
* Add work/ to clean list
* Hide echo commands in window
* The word test is reserved in pytest only for tests, doen't use it for any thing else, like blocks
* Add myhdl.vpi to clean
* Mark these tests as xfail, for now,
* Fix and unmark xfail 2 tests
* Add black support
* Remove python2 only testing
* Need to relook at this test, it performs differently for verilog and vhdl
* Add RTL files to the list
* Need to relook at this test, it performs differently for verilog and vhdl
* Upgrade to DeprecationWarnings
* Initial checkin with passing flow for new convert VHDL/Verilog, there are a few xfail tests that need to be debugged
* Add more examples for the Deprecation cases, toVHDL and toVerilog
* Fix deprecations catching
* Fix pytest to use pytest.ini
* Add pypi release steps
* Fix intbv error
* Fix indent
* Update to do a release
* Add checkout to step
* Update Python versions
* Add dependancy on tag on push
2022-12-17 12:21:08 +00:00
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'Programming Language :: Python :: 3.8',
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'Programming Language :: Python :: 3.9',
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'Programming Language :: Python :: 3.10',
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2019-03-12 17:51:12 +02:00
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'Programming Language :: Python :: 3 :: Only',
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2015-03-24 03:49:56 -04:00
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]
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)
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