2016-03-10 20:27:07 +01:00
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import myhdl
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2006-02-21 09:24:55 +00:00
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from myhdl import *
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2006-09-19 19:58:18 +00:00
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from myhdl.conversion import analyze
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2006-02-21 09:24:55 +00:00
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2024-12-21 17:21:11 +01:00
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2006-02-21 09:24:55 +00:00
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def dff(q, d, clk):
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@always(clk.posedge)
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2024-12-21 17:21:11 +01:00
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def comb():
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2006-02-21 09:24:55 +00:00
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q.next = d
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2024-12-21 17:21:11 +01:00
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return comb
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2006-02-21 09:24:55 +00:00
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from random import randrange
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2024-12-21 17:21:11 +01:00
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2006-02-21 09:24:55 +00:00
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def test_dff():
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2024-12-21 17:21:11 +01:00
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2006-02-21 09:24:55 +00:00
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q, d, clk = [Signal(bool(0)) for i in range(3)]
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2024-12-21 17:21:11 +01:00
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2006-02-21 09:24:55 +00:00
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dff_inst = dff(q, d, clk)
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@always(delay(10))
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def clkgen():
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clk.next = not clk
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@always(clk.negedge)
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def stimulus():
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d.next = randrange(2)
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return dff_inst, clkgen, stimulus
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2024-12-21 17:21:11 +01:00
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2006-02-21 09:24:55 +00:00
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def simulate(timesteps):
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2012-04-25 21:25:04 +02:00
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traceSignals.timescale = "1ps"
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2006-02-21 09:24:55 +00:00
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tb = traceSignals(test_dff)
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sim = Simulation(tb)
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sim.run(timesteps)
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2016-03-03 07:46:19 +05:30
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sim.quit()
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2006-02-21 09:24:55 +00:00
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2024-12-21 17:21:11 +01:00
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2006-02-21 09:24:55 +00:00
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simulate(2000)
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2024-12-21 17:21:11 +01:00
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2006-02-21 09:24:55 +00:00
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def convert():
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q, d, clk = [Signal(bool(0)) for i in range(3)]
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toVerilog(dff, q, d, clk)
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2006-09-19 19:58:18 +00:00
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analyze(dff, q, d, clk)
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2024-12-21 17:21:11 +01:00
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2006-02-21 09:24:55 +00:00
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convert()
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2024-12-21 17:21:11 +01:00
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