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from myhdl import *
ACTIVE_LOW = 0
FRAME_SIZE = 8
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t_State = enum('SEARCH', 'CONFIRM', 'SYNC')
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def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
""" Framing control FSM.
SOF -- start-of-frame output bit
state -- FramerState output
syncFlag -- sync pattern found indication input
clk -- clock input
reset_n -- active low reset
"""
index = Signal(0) # position in frame
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@always(clk.posedge, reset_n.negedge)
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def FSM():
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if reset_n == ACTIVE_LOW:
SOF.next = 0
index.next = 0
state.next = t_State.SEARCH
else:
index.next = (index + 1) % FRAME_SIZE
SOF.next = 0
if state == t_State.SEARCH:
index.next = 1
if syncFlag:
state.next = t_State.CONFIRM
elif state == t_State.CONFIRM:
if index == 0:
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if syncFlag:
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state.next = t_State.SYNC
else:
state.next = t_State.SEARCH
elif state == t_State.SYNC:
if index == 0:
if not syncFlag:
state.next = t_State.SEARCH
SOF.next = (index == FRAME_SIZE-1)
else:
raise ValueError("Undefined state")
return FSM
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def testbench():
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SOF = Signal(bool(0))
syncFlag = Signal(bool(0))
clk = Signal(bool(0))
reset_n = Signal(bool(1))
state = Signal(t_State.SEARCH)
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framectrl = FramerCtrl(SOF, state, syncFlag, clk, reset_n)
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@always(delay(10))
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def clkgen():
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clk.next = not clk
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@instance
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def stimulus():
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for i in range(3):
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yield clk.posedge
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for n in (12, 8, 8, 4):
syncFlag.next = 1
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yield clk.posedge
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syncFlag.next = 0
for i in range(n-1):
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yield clk.posedge
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raise StopSimulation
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return framectrl, clkgen, stimulus
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def main():
tb_fsm = traceSignals(testbench)
sim = Simulation(tb_fsm)
sim.run()
if __name__ == '__main__':
main()