2008-11-07 14:57:56 +01:00
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Release 0.6dev10
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----------------
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2006-10-04 15:15:32 +00:00
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2006-05-01 10:42:39 +00:00
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Release 0.5.1 1-May-2006
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2006-04-14 13:13:05 +00:00
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-------------------------
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2006-04-27 11:01:34 +00:00
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Maintenance release for 0.5.
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See the bug tracker for fixed issues.
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2006-04-14 13:13:05 +00:00
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2005-12-27 14:56:52 +00:00
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Release 0.5 29-Dec-2005
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2005-10-07 08:24:44 +00:00
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-----------------------
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2005-12-28 13:06:39 +00:00
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Full details about new features and changes can be found here:
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2005-12-27 14:33:57 +00:00
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http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5
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2005-10-07 08:24:44 +00:00
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2004-12-28 17:14:39 +00:00
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Release 0.4.1 29-Dec-2004
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-------------------------
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* Maintenance release that solves most outstanding issues
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and implements some feature requests.
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See the SourceForge Bug and RFE Trackers for details.
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(Use the group 'MyHDL 0.4' to find the relevant issues.)
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More info can also be found on the mailing list.
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* Added cosimulation support for the cver Verilog simulator.
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Note: the documentation was not modified in this release.
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2004-02-04 16:01:23 +00:00
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Release 0.4 4-Feb-2004
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----------------------
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2004-02-02 21:52:41 +00:00
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2004-12-28 17:14:39 +00:00
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* Conversion to Verilog to provide a path to implementation
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2004-02-02 21:52:41 +00:00
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2005-12-27 14:33:57 +00:00
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For full details about the changes, consult:
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http://www.jandecaluwe.com/Tools/MyHDL/whatsnew04/whatsnew04.html
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2004-02-02 21:52:41 +00:00
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2003-08-23 18:07:37 +00:00
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Release 0.3 30-Aug-2003
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2003-08-22 07:49:18 +00:00
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-----------------------
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* VCD output for waveform viewing
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* Enumeration types support
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2003-08-28 15:43:17 +00:00
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* Inferring the sensitivity list for combinatorial logic
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2003-08-22 07:49:18 +00:00
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* Inferring the list of instances
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* Inferring the list of processes
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* Class intbv enhancements
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* Function concat()
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* Python 2.3 support
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2005-12-27 14:33:57 +00:00
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For full details about the changes, consult:
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http://www.jandecaluwe.com/Tools/MyHDL/whatsnew03/whatsnew03.html
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2003-08-22 07:49:18 +00:00
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2003-05-14 09:12:21 +00:00
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Release 0.2 19-May-2003
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2003-03-07 11:58:10 +00:00
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-----------------------
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2003-05-14 09:12:21 +00:00
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* Added cosimulation support to MyHDL.
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2003-05-14 10:43:02 +00:00
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A PLI interface module to the Icarus Verilog simulator is included.
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2003-05-14 09:12:21 +00:00
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Release 0.1 7-Mar-2003
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----------------------
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* Initial public release
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