2004-03-02 11:11:31 +00:00
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A working cver installation is required.
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Use the makefile corresponding to your platform to generate a 'myhdl.so'
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PLI module. Currently, the following makefiles are available:
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makefile.lnx - for Linux
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To test whether it works, go to the 'test' subdirectory and run the
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tests with 'python test_all.py'.
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2004-03-19 12:15:36 +00:00
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For co-simulation with MyHDL, 'cver' should be run with the 'myhdl_vpi.so'
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2004-03-02 11:11:31 +00:00
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PLI module, using the '+loadvpi' option, and with the 'vpi_compat_bootstrap'
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routine as the bootstrap routine. The Verilog code should contain the
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appropriate calls to the '$to_myhdl' and 'from_myhdl' tasks.
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2004-03-19 12:15:36 +00:00
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The 'myhdl_vpi.c' module was developed and verified with cver version
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2004-03-02 11:11:31 +00:00
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GPLCVER_1.10f on Linux.
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