2003-04-24 19:24:37 +00:00
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from __future__ import generators
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import unittest
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from unittest import TestCase
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2003-05-07 16:52:57 +00:00
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import random
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2003-04-24 19:24:37 +00:00
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from random import randrange
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2003-05-07 16:52:57 +00:00
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random.seed(2)
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2003-04-24 19:24:37 +00:00
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2003-07-07 21:37:58 +00:00
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#import psyco
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#psyco.profile()
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2003-04-24 19:24:37 +00:00
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from myhdl import Simulation, StopSimulation, Signal, \
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2003-05-07 16:52:57 +00:00
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delay, intbv, negedge, posedge, now
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2003-04-24 19:24:37 +00:00
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from inc import inc
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ACTIVE_LOW, INACTIVE_HIGH = 0, 1
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class TestInc(TestCase):
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2003-05-12 16:57:17 +00:00
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def clockGen(self, clock):
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while 1:
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yield delay(10)
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clock.next = not clock
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def stimulus(self, enable, clock, reset):
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reset.next = ACTIVE_LOW
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yield negedge(clock)
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reset.next = INACTIVE_HIGH
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2003-06-02 14:38:03 +00:00
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for i in range(1000):
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2003-05-12 16:57:17 +00:00
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enable.next = min(1, randrange(5))
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yield negedge(clock)
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raise StopSimulation
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def check(self, count, enable, clock, reset, n):
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expect = 0
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yield posedge(reset)
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self.assertEqual(count, expect)
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while 1:
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yield posedge(clock)
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if enable:
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expect = (expect + 1) % n
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yield delay(1)
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# print "%d count %s expect %s" % (now(), count, expect)
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self.assertEqual(count, expect)
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2003-05-09 21:11:41 +00:00
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def bench(self):
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2003-04-24 19:24:37 +00:00
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n = 253
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count, enable, clock, reset = [Signal(intbv(0)) for i in range(4)]
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INC_1 = inc(count, enable, clock, reset, n=n)
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2003-05-12 16:57:17 +00:00
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CLK_1 = self.clockGen(clock)
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ST_1 = self.stimulus(enable, clock, reset)
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CH_1 = self.check(count, enable, clock, reset, n=n)
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sim = Simulation(INC_1, CLK_1, ST_1, CH_1)
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2003-05-09 21:11:41 +00:00
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return sim
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def test1(self):
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""" Check increment operation """
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sim = self.bench()
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sim.run(quiet=1)
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2003-06-02 14:38:03 +00:00
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def test2(self):
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2003-05-09 21:11:41 +00:00
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""" Check increment operation with suspended simulation runs """
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sim = self.bench()
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while sim.run(duration=randrange(1, 6), quiet=1):
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pass
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2003-04-24 19:24:37 +00:00
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if __name__ == '__main__':
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unittest.main()
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