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55 lines
1.3 KiB
ReStructuredText
55 lines
1.3 KiB
ReStructuredText
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.. currentmodule:: myhdl
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.. _new09:
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***********************
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What's new in MyHDL 0.9
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***********************
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:Author:
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Interfaces
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===========
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Rationale
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---------
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Complex designs often have many signals (ports) that
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are passed to different levels of hierarchy. Typically
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many of the signals can logically be grouped together.
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Grouping the signals into an *interface* simplifies the
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code, improves efficiency, and reduces errors.
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Previous versions supported /interfaces/ for modeling
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and for conversion if the **attributes** were locally
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referenced in a MyHDL module. The proposed solution
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will convert an example like the following:
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def complex_mult(clock,reset,a,b,c):
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@always_seq(clock.posedge,reset=reset)
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def rtl_mult():
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c.real.next = (a.real*b.real) - (a.imag*b.imag)
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c.imag.next = (a.real*b.imag) + (a.imag*b.real)
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return rtl_mult
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Solution
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--------
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The proposed solution is to create uniques names for
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attributes which are type Signal and used by a module.
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The converter will create a unique name by using the
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name of the parent and the name of the attribute along
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with the name of the MyHDL module instance (if applicable).
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Conversion
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----------
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See also
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--------
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For additional information see the original proposal `mep-107`_.
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.. _mep-107: http://http://myhdl.org/doku.php/meps:mep-107
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