myhdl/doc/MyHDL.tex

\documentclass{manual}
\usepackage{palatino}
\renewcommand{\ttdefault}{cmtt}
\renewcommand{\sfdefault}{cmss}
\newcommand{\myhdl}{{MyHDL}}

\title{The \myhdl\ manual}

\input{boilerplate}

\begin{document}

\maketitle

\input{copyright}

\begin{abstract}

\noindent

\myhdl\ is a Python package for using Python as a hardware description
language. Popular hardware description languages, like Verilog and
VHDL, are compiled languages. \myhdl\ with Python can be viewed as a
"scripting language" counterpart of such languages. However, Python is
more accurately described as a very high level language
(VHLL). \myhdl\ users have access to the amazing power and elegance of
Python for their modeling work.

The key idea behind \myhdl\ is to use Python generators to model the
concurrency required in hardware descriptions. As generators are a
recent Python feature, \myhdl\ requires Python 2.2.2 or higher.

\myhdl\ 0.1 is the initial public release of the package. It can be
used to experiment with high level modeling, and with verification
techniques such as unit testing. But the primary goal is to generate
interest and to solicit feedback.

In a future release, \myhdl\ will hopefully be coupled to hardware
simulators for languages such as Verilog and VHDL. That would turn
Python into a powerful hardware verification language.

\end{abstract}

\tableofcontents

\input{background.tex}
\input{informal.tex}
\input{modeling.tex}
\input{unittest.tex}
\input{reference.tex}

\end{document}