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jand 2004-01-28 23:07:16 +00:00
parent ced30e3984
commit 0002a5d678
1 changed files with 1 additions and 1 deletions
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doc/whatsnew04/whatsnew04.tex
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@ -281,7 +281,7 @@ width = 8
graycnt = Signal(intbv()[width:])
enable, clock, reset = [Signal(bool()) for i in range(3)]
GRAY_INC_1 = toVerilog(GrayIncReg, graycnt, enable, clock, reset, width)
GRAY_INC_REG_1 = toVerilog(GrayIncReg, graycnt, enable, clock, reset, width)
\end{verbatim}
The Verilog output module looks as follows: