diff --git a/myhdl/_toVHDL/_convert.py b/myhdl/_toVHDL/_convert.py index d3fbc3fa..c1abf5e7 100644 --- a/myhdl/_toVHDL/_convert.py +++ b/myhdl/_toVHDL/_convert.py @@ -304,42 +304,54 @@ class _ConvertVisitor(_ToVerilogMixin): size = int(math.ceil(math.log(n+1,2))) + 1 # sign bit! self.write("%s'sd" % size) - def writeDeclaration(self, obj, name, dir, endchar=";"): - if dir: dir = dir + ' ' - if type(obj) is bool: - self.write("%s%s: std_logic" % (dir, name)) - elif isinstance(obj, EnumItemType): - self.write("%s%s: %s" % (dir, name, obj._type._name)) - elif isinstance(obj, int): - if dir == "input ": - self.write("input %s;" % name) - self.writeline() - self.write("variable %s: integer" % name) + def writeDeclaration(self, obj, name, kind="", dir="", endchar=";", constr=True): + if isinstance(obj, EnumItemType): + tipe = obj._type._name elif isinstance(obj, _Ram): - self.write("reg [%s-1:0] %s [0:%s-1]" % (obj.elObj._nrbits, name, obj.depth)) - elif hasattr(obj, '_nrbits'): - s = "unsigned" - if isinstance(obj, (intbv, Signal)): - if obj._min is not None and obj._min < 0: - s = "signed " - if dir == "in ": - self.write("%s: %s %s(%s-1 downto 0)" % (name, dir, s, obj._nrbits)) - else: - self.write("%s%s: %s(%s-1 downto 0)" % (dir, name, s, obj._nrbits)) + tipe = "reg [%s-1:0] %s [0:%s-1]" % (obj.elObj._nrbits, name, obj.depth) else: - raise AssertionError("var %s has unexpected type %s" % (name, type(obj))) - # initialize regs - # if dir == 'reg ' and not isinstance(obj, _Ram): - # disable for cver - if False: - if isinstance(obj, EnumItemType): - inival = obj._toVHDL() - else: - inival = int(obj) - self.write(" = %s;" % inival) - else: - self.write(endchar) - + vhdlObj = inferVhdlObj(obj) + tipe = vhdlObj.toStr(constr) + if kind: kind += " " + if dir: dir += " " + self.write("%s%s: %s%s%s" % (kind, name, dir, tipe, endchar)) + + +## def writeDeclaration(self, obj, name, dir, endchar=";"): +## if dir: dir = dir + ' ' +## if type(obj) is bool: +## self.write("%s%s: std_logic" % (dir, name)) +## elif isinstance(obj, EnumItemType): +## self.write("%s%s: %s" % (dir, name, obj._type._name)) +## elif isinstance(obj, int): +## if dir == "input ": +## self.write("input %s;" % name) +## self.writeline() +## self.write("variable %s: integer" % name) +## elif isinstance(obj, _Ram): +## self.write("reg [%s-1:0] %s [0:%s-1]" % (obj.elObj._nrbits, name, obj.depth)) +## elif hasattr(obj, '_nrbits'): +## s = "unsigned" +## if isinstance(obj, (intbv, Signal)): +## if obj._min is not None and obj._min < 0: +## s = "signed " +## if dir == "in ": +## self.write("%s: %s %s(%s-1 downto 0)" % (name, dir, s, obj._nrbits)) +## else: +## self.write("%s%s: %s(%s-1 downto 0)" % (dir, name, s, obj._nrbits)) +## else: +## raise AssertionError("var %s has unexpected type %s" % (name, type(obj))) +## # initialize regs +## # if dir == 'reg ' and not isinstance(obj, _Ram): +## # disable for cver +## if False: +## if isinstance(obj, EnumItemType): +## inival = obj._toVHDL() +## else: +## inival = int(obj) +## self.write(" = %s;" % inival) +## else: +## self.write(endchar) def writeDeclarations(self): if self.ast.hasPrint: @@ -349,7 +361,7 @@ class _ConvertVisitor(_ToVerilogMixin): if isinstance(obj, _loopInt): continue # hack for loop vars self.writeline() - self.writeDeclaration(obj, name, "variable") + self.writeDeclaration(obj, name, kind="variable") def indent(self): self.ind += ' ' * 4 @@ -358,9 +370,9 @@ class _ConvertVisitor(_ToVerilogMixin): self.ind = self.ind[:-4] def binaryOp(self, node, op=None): - if isinstance(node.vhdlObj, vhdl_integer): - node.left.vhdlObj = vhdl_integer() - node.right.vhdlObj = vhdl_integer() + if isinstance(node.vhdlObj, vhdl_int): + node.left.vhdlObj = vhdl_int() + node.right.vhdlObj = vhdl_int() context = None if node.signed: context = _context.SIGNED @@ -451,6 +463,8 @@ class _ConvertVisitor(_ToVerilogMixin): def visitAssign(self, node, *args): assert len(node.nodes) == 1 + lhs = node.nodes[0] + rhs = node.expr # shortcut for expansion of ROM in case statement if isinstance(node.expr, astNode.Subscript) and \ isinstance(node.expr.expr.obj, _Rom): @@ -473,22 +487,32 @@ class _ConvertVisitor(_ToVerilogMixin): self.isSigAss = False else: self.write(' := ') - self.write('"%s";' % bin(n, size)) + if isinstance(lhs.vhdlObj, vhdl_std_logic): + self.write("'%s';" % n) + elif isinstance(lhs.vhdlObj, vhdl_int): + self.write("%s;" % n) + else: + self.write('"%s";' % bin(n, size)) self.dedent() self.writeline() self.write("end case;") return # default behavior convOpen, convClose = "", "" - lhs = node.nodes[0] - rhs = node.expr if isinstance(lhs.vhdlObj, vhdl_unsigned): if isinstance(rhs.vhdlObj, vhdl_unsigned) and \ (lhs.vhdlObj.size == rhs.vhdlObj.size): pass else: convOpen, convClose = "to_unsigned(", ", %s)" % lhs.vhdlObj.size - rhs.vhdlObj = vhdl_integer() + rhs.vhdlObj = vhdl_int() + elif isinstance(lhs.vhdlObj, vhdl_signed): + if isinstance(rhs.vhdlObj, vhdl_signed) and \ + (lhs.vhdlObj.size == rhs.vhdlObj.size): + pass + else: + convOpen, convClose = "to_signed(", ", %s)" % lhs.vhdlObj.size + rhs.vhdlObj = vhdl_int() elif isinstance(lhs.vhdlObj, vhdl_std_logic): rhs.vhdlObj = vhdl_std_logic() self.visit(node.nodes[0]) @@ -574,10 +598,10 @@ class _ConvertVisitor(_ToVerilogMixin): self.write(f.__name__) if node.args: self.write(opening) - self.visit(node.args[0]) + self.visit(node.args[0], *args) for arg in node.args[1:]: self.write(sep) - self.visit(arg) + self.visit(arg, *args) self.write(closing) if hasattr(node, 'ast'): if node.ast.kind == _kind.TASK: @@ -612,6 +636,8 @@ class _ConvertVisitor(_ToVerilogMixin): self.write("'%s'" % node.value) ## elif target._type is intbv: ## self.write('"%s"' % bin(node.value, len(target))) + elif isinstance(node.vhdlObj, vhdl_boolean): + self.write("%s" % bool(node.value)) else: self.write(node.value) @@ -797,20 +823,27 @@ class _ConvertVisitor(_ToVerilogMixin): addSignBit = isMixedExpr s = n obj = self.ast.vardict[n] - if isinstance(obj, intbv) and isinstance(node.vhdlObj, vhdl_integer): + if isinstance(obj, intbv) and isinstance(node.vhdlObj, vhdl_int): s = "to_integer(%s)" % n elif n in self.ast.argnames: assert n in self.ast.symdict addSignBit = isMixedExpr - s = n + obj = self.ast.symdict[n] + vhdlObj = inferVhdlObj(obj) + if isinstance(vhdlObj, vhdl_std_logic) and isinstance(node.vhdlObj, vhdl_boolean): + s = "%s = '1'" % n + else: + s = n elif n in self.ast.symdict: obj = self.ast.symdict[n] #obj = node.obj if isinstance(obj, bool): s = "'%s'" % int(obj) elif isinstance(obj, (int, long)): - if isinstance(node.vhdlObj, vhdl_integer): + if isinstance(node.vhdlObj, vhdl_int): s = "%s" % int(obj) + elif isinstance(node.vhdlObj, vhdl_std_logic): + s = "'%s'" % int(obj) else: s = '"%s"' % bin(obj, node.vhdlObj.size) elif isinstance(obj, Signal): @@ -827,7 +860,7 @@ class _ConvertVisitor(_ToVerilogMixin): elif context == _context.BOOLEAN and \ obj._type is bool: s = "%s = '1'" % str(obj) - elif (obj._type is intbv) and isinstance(node.vhdlObj, vhdl_integer): + elif (obj._type is intbv) and isinstance(node.vhdlObj, vhdl_int): s = "to_integer(%s)" % str(obj) else: addSignBit = isMixedExpr @@ -846,11 +879,11 @@ class _ConvertVisitor(_ToVerilogMixin): self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj))) else: raise AssertionError("name ref: %s" % n) - if addSignBit: - self.write("$signed({1'b0, ") +## if addSignBit: +## self.write("$signed({1'b0, ") self.write(s) - if addSignBit: - self.write("})") +## if addSignBit: +## self.write("})") def visitPass(self, node, *args): self.write("null;") @@ -1181,9 +1214,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor): self.returnLabel = _Label("RETURN") def writeOutputDeclaration(self): - obj = self.ast.returnObj - # self.writeDeclaration(obj, self.ast.name, dir='') - self.write(inferVhdlObj(obj)) + self.write(self.ast.vhdlObj.toStr(constr=False)) def writeInputDeclarations(self): endchar = "" @@ -1192,7 +1223,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor): enchar = ";" obj = self.ast.symdict[name] self.writeline() - self.writeDeclaration(obj, name, "in", endchar="") + self.writeDeclaration(obj, name, dir="in", constr=False, endchar="") def visitFunction(self, node, *args): self.write("function %s(" % self.ast.name) @@ -1201,8 +1232,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor): self.writeline() self.write(") return ") self.writeOutputDeclaration() - self.writeline() - self.write("is") + self.write(" is") self.writeDeclarations() self.dedent() self.writeline() @@ -1227,30 +1257,40 @@ class _ConvertTaskVisitor(_ConvertVisitor): self.returnLabel = _Label("RETURN") def writeInterfaceDeclarations(self): + endchar = "" for name in self.ast.argnames: + self.write(endchar) + endchar = ";" obj = self.ast.symdict[name] output = name in self.ast.outputs input = name in self.ast.inputs inout = input and output - dir = (inout and "inout") or (output and "output") or "input" + dir = (inout and "inout") or (output and "out") or "in" self.writeline() - self.writeDeclaration(obj, name, dir) + self.writeDeclaration(obj, name, dir=dir, constr=False, endchar="") def visitFunction(self, node, *args): - self.write("task %s;" % self.ast.name) - self.indent() - self.writeInterfaceDeclarations() + self.write("procedure %s" % self.ast.name) + if self.ast.argnames: + self.write("(") + self.indent() + self.writeInterfaceDeclarations() + self.write(") ") + self.write("is") self.writeDeclarations() self.dedent() self.writeline() - self.write("begin: %s" % self.returnLabel) + self.write("begin") self.indent() + print 'here' + print node.code.nodes[0] + t = node.code.nodes[0].tests[0][0] + print t + print t.vhdlObj self.visit(node.code) self.dedent() self.writeline() - self.write("end") - self.writeline() - self.write("endtask") + self.write("end procedure %s;" % self.ast.name) self.writeline(2) @@ -1261,39 +1301,51 @@ class vhdl_type(object): class vhdl_std_logic(vhdl_type): def __init__(self, size=0): self.size = 1 - def __str__(self): + def toStr(self, constr=True): return 'std_logic' class vhdl_boolean(vhdl_type): def __init__(self, size=0): self.size = 1 - def __str__(self): + def toStr(self, constr=True): return 'boolean' class vhdl_unsigned(vhdl_type): - def __str__(self): - return "unsigned(%s downto 0)" % (self.size-1) + def toStr(self, constr=True): + if constr: + return "unsigned(%s downto 0)" % (self.size-1) + else: + return "unsigned" class vhdl_signed(vhdl_type): - def __str__(self): - return "signed(%s downto 0)" % (self.size-1) + def toStr(self, constr=True): + if constr: + return "signed(%s downto 0)" % (self.size-1) + else: + return "signed" -class vhdl_integer(vhdl_type): - def __str__(self): +class vhdl_int(vhdl_type): + def toStr(self, constr=True): return "integer" class _loopInt(int): pass -def maxType(t1, t2): - if t1 is vhdl_signed or t2 is vhdl_signed: - return vhdl_signed - elif t1 is vhdl_unsigned or t2 is vhdl_unsigned: - return vhdl_unsigned - elif t1 is vhdl_std_logic or t2 is vhdl_std_logic: - return vhdl_std_logic - elif t1 is vhdl_integer or t2 is vhdl_integer: - return vhdl_integer +def maxType(o1, o2): + s1 = s2 = 0 + if isinstance(o1, vhdl_type): + s1 = o1.size + if isinstance(o2, vhdl_type): + s2 = o2.size + s = max(s1, s2) + if isinstance(o1, vhdl_signed) or isinstance(o2, vhdl_signed): + return vhdl_signed(s) + elif isinstance(o1, vhdl_unsigned) or isinstance(o2, vhdl_unsigned): + return vhdl_unsigned(s) + elif isinstance(o1, vhdl_std_logic) or isinstance(o2, vhdl_std_logic): + return vhdl_std_logic() + elif isinstance(o1, vhdl_int) or isinstance(o2, vhdl_int): + return vhdl_int() else: return None @@ -1309,7 +1361,7 @@ def inferVhdlObj(obj): isinstance(obj, bool): vhdlObj = vhdl_std_logic() elif isinstance(obj, (int, long)): - vhdlObj = vhdl_integer() + vhdlObj = vhdl_int() return vhdlObj @@ -1326,34 +1378,32 @@ class _AnnotateTypesVisitor(_ToVerilogMixin): fn = node.node assert isinstance(fn, astNode.Name) f = self.getObj(fn) - if f is intbv: - return + node.vhdlObj = inferVhdlObj(node.obj) self.visitChildNodes(node) if f is concat: s = 0 for a in node.args: s += a.vhdlObj.size node.vhdlObj = vhdl_unsigned(s) + elif f is intbv: + node.vhdlObj = vhdl_int() elif f is len: - node.vhdlObj = vhdl_integer() + node.vhdlObj = vhdl_int() elif hasattr(node, 'ast'): v = _AnnotateTypesVisitor(node.ast) compiler.walk(node.ast, v) - vhdlObj = inferVhdlObj(node.ast.returnObj) - node.vhdlObj = self.ast.vhdlObj = vhdlObj + node.vhdlObj = node.ast.vhdlObj = inferVhdlObj(node.ast.returnObj) def visitCompare(self, node): node.vhdlObj = vhdl_boolean() self.visitChildNodes(node) expr = node.expr op, code = node.ops[0] - s = max(expr.vhdlObj.size, code.vhdlObj.size) - t = maxType(type(expr.vhdlObj), type(code.vhdlObj)) - expr.vhdlObj = t(s) - code.vhdlObj = t(s) + o = maxType(expr.vhdlObj, code.vhdlObj) + expr.vhdlObj = code.vhdlObj = o def visitConst(self, node): - node.vhdlObj = vhdl_integer() + node.vhdlObj = vhdl_int() def visitFor(self, node): self.visitChildNodes(node) @@ -1361,6 +1411,10 @@ class _AnnotateTypesVisitor(_ToVerilogMixin): # make it possible to detect loop variable self.ast.vardict[var] = _loopInt() + def visitGetattr(self, node): + self.visitChildNodes(node) + node.vhdlObj = None + def visitName(self, node): node.vhdlObj = inferVhdlObj(node.obj) @@ -1374,25 +1428,25 @@ class _AnnotateTypesVisitor(_ToVerilogMixin): self.visit(node.right) r = node.right.vhdlObj l = node.left.vhdlObj - if isinstance(r, vhdl_signed) and isinstance(l, vhdl_signed): + if isinstance(r, vhdl_int) and isinstance(l, vhdl_int): + node.vhdlObj = vhdl_int() + elif isinstance(r, (vhdl_signed, vhdl_int)) and isinstance(l, (vhdl_signed, vhdl_int)): node.vhdlObj = vhdl_signed(max(l.size, r.size)) - elif isinstance(r, vhdl_unsigned) and isinstance(l, vhdl_unsigned): + elif isinstance(r, (vhdl_unsigned, vhdl_int)) and isinstance(l, (vhdl_unsigned, vhdl_int)): node.vhdlObj = vhdl_unsigned(max(l.size, r.size)) else: - node.vhdlObj = vhdl_integer() + node.vhdlObj = vhdl_int() visitAdd = visitSub = visitMod = binaryOp def multiBitOp(self, node): self.visitChildNodes(node) - t = vhdl_std_logic - s = 0 + o = None for n in node.nodes: - s = max(s, n.vhdlObj.size) - t = maxType(t, type(n.vhdlObj)) + o = maxType(o, n.vhdlObj) for n in node.nodes: - n.vhdlObj = t(s) - node.vhdlObj = t(s) + n.vhdlObj = o + node.vhdlObj = o def multiBoolOp(self, node): self.visitChildNodes(node) @@ -1402,8 +1456,13 @@ class _AnnotateTypesVisitor(_ToVerilogMixin): visitBitand = visitBitor = visitBitxor = multiBitOp def visitNot(self, node): - node.vhdlObj = None self.visit(node.expr) + node.vhdlObj = vhdl_boolean() + + def visitIf(self, node): + self.visitChildNodes(node) + for test, suite in node.tests: + test.vhdlObj = vhdl_boolean() def visitSlice(self, node): self.visitChildNodes(node) @@ -1423,6 +1482,17 @@ class _AnnotateTypesVisitor(_ToVerilogMixin): self.visitChildNodes(node) node.vhdlObj = vhdl_std_logic() + def unaryOp(self, node): + self.visit(node.expr) + node.vhdlObj = node.expr.vhdlObj + + visitUnaryAdd = visitUnarySub = unaryOp + + def visitWhile(self, node): + self.visitChildNodes(node) + node.test.vhdlObj = vhdl_boolean() + + def _annotateTypes(genlist): diff --git a/myhdl/_toVerilog/_analyze.py b/myhdl/_toVerilog/_analyze.py index 4084cdb0..d6449244 100644 --- a/myhdl/_toVerilog/_analyze.py +++ b/myhdl/_toVerilog/_analyze.py @@ -131,7 +131,7 @@ def _analyzeGens(top, absnames): s = re.sub(r"@.*", "", s) s = s.lstrip() ast = compiler.parse(s) - print ast + #print ast ast.sourcefile = inspect.getsourcefile(f) ast.lineoffset = inspect.getsourcelines(f)[1]-1 ast.symdict = f.func_globals.copy() @@ -159,7 +159,7 @@ def _analyzeGens(top, absnames): s = re.sub(r"@.*", "", s) s = s.lstrip() ast = compiler.parse(s) - print ast + #print ast ast.sourcefile = inspect.getsourcefile(f) ast.lineoffset = inspect.getsourcelines(f)[1]-1 ast.symdict = f.f_globals.copy() @@ -518,6 +518,7 @@ class _AnalyzeVisitor(_ToVerilogMixin): compiler.walk(ast, v) v = _AnalyzeFuncVisitor(ast, node.args) compiler.walk(ast, v) + node.obj = ast.returnObj node.ast = ast for i, arg in enumerate(node.args): if isinstance(arg, astNode.Keyword): @@ -785,6 +786,13 @@ class _AnalyzeVisitor(_ToVerilogMixin): self.raiseError(node, _error.UnsupportedYield) senslist = [n.obj] node.senslist = senslist + +## def visitModule(self, node, *args): +## self.visit(node.node) +## for n in self.ast.inputs: +## s = self.ast.sigdict[n] +## s._read = True + class _AnalyzeBlockVisitor(_AnalyzeVisitor): diff --git a/myhdl/test/toVHDL/test_bin2gray.py b/myhdl/test/toVHDL/test_bin2gray.py index e7bcbc40..e32d5f2c 100644 --- a/myhdl/test/toVHDL/test_bin2gray.py +++ b/myhdl/test/toVHDL/test_bin2gray.py @@ -71,7 +71,8 @@ def bin2grayBench(width, bin2gray): ## sim = self.bench(width=8, bin2gray=bin2gray2) ## Simulation(sim).run() - -verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray) -verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray2) +def test1(): + assert verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray) == 0 +def test2(): + assert verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray2) == 0 diff --git a/myhdl/test/toVHDL/test_dec.py b/myhdl/test/toVHDL/test_dec.py new file mode 100644 index 00000000..8623f96e --- /dev/null +++ b/myhdl/test/toVHDL/test_dec.py @@ -0,0 +1,220 @@ +import os +path = os.path +import random +from random import randrange +random.seed(2) + +from myhdl import * +from myhdl.test import verifyConversion + +ACTIVE_LOW, INACTIVE_HIGH = 0, 1 + + +def decRef(count, enable, clock, reset, n): + """ Decrementer with enable. + + count -- output + enable -- control input, decrement when 1 + clock -- clock input + reset -- asynchronous reset input + n -- counter max value + """ + while 1: + yield clock.posedge, reset.negedge + if reset == ACTIVE_LOW: + count.next = 0 + else: + if enable: + if count == -n: + count.next = n-1 + else: + count.next = count - 1 + + +def dec(count, enable, clock, reset, n): + """ Decrementer with enable. + + count -- output + enable -- control input, decrement when 1 + clock -- clock input + reset -- asynchronous reset input + n -- counter max value + """ + def decProcess(): + while 1: + yield clock.posedge, reset.negedge + if reset == ACTIVE_LOW: + count.next = 0 + else: + if enable: + if count == -n: + count.next = n-1 + else: + count.next = count - 1 + return decProcess() + + +def decFunc(count, enable, clock, reset, n): + + def decFuncFunc(cnt): + count_next = intbv(0, min=-n, max=n) + if cnt == -n: + count_next[:] = n-1 + else: + count_next[:] = cnt - 1 + return count_next + + @always(clock.posedge, reset.negedge) + def decFuncGen(): + if reset == ACTIVE_LOW: + count.next = 0 + else: + if enable: + count.next = decFuncFunc(count) + + return decFuncGen + + +def decTask(count, enable, clock, reset, n): + + def decTaskFunc(cnt, enable, reset, n): + if enable: + if cnt == -n: + cnt[:] = n-1 + else: + cnt[:] = cnt - 1 + + def decTaskGen(): + cnt = intbv(0, min=-n, max=n) + while 1: + yield clock.posedge, reset.negedge + if reset == ACTIVE_LOW: + cnt[:] = 0 + count.next = 0 + else: + # print count + decTaskFunc(cnt, enable, reset, n) + count.next = cnt + + return decTaskGen() + + +def decTaskFreeVar(count, enable, clock, reset, n): + + def decTaskFunc(): + if enable: + if count == -n: + count.next = n-1 + else: + count.next = count - 1 + + def decTaskGen(): + while 1: + yield clock.posedge, reset.negedge + if reset == ACTIVE_LOW: + count.next = 0 + else: + # print count + decTaskFunc() + + return decTaskGen() + + + +def DecBench(dec): + + m = 8 + n = 2 ** (m-1) + + count = Signal(intbv(0, min=-n, max=n)) + count_v = Signal(intbv(0, min=-n, max=n)) + enable = Signal(bool(0)) + clock, reset = [Signal(bool(1)) for i in range(2)] + + @instance + def clockGen(): + yield delay(10) + clock.next = 0 + while 1: + yield delay(10) + clock.next = not clock + + enables = tuple([min(1, randrange(5)) for i in range(1000)]) + @instance + def stimulus(): + reset.next = INACTIVE_HIGH + yield clock.negedge + reset.next = ACTIVE_LOW + yield clock.negedge + reset.next = INACTIVE_HIGH + for i in range(1000): + enable.next = 1 + yield clock.negedge + for i in range(len(enables)): + enable.next = enables[i] + yield clock.negedge + raise StopSimulation + + @instance + def check(): + yield reset.posedge + print count + while 1: + yield clock.posedge + yield delay(1) + print count + + dec_inst = dec(count, enable, clock, reset, n=n) + + return dec_inst, clockGen, stimulus, check + + + +def testDecRef(): + assert verifyConversion(DecBench, decRef) == 0 + +def testDec(): + assert verifyConversion(DecBench, dec) == 0 + +def testDecFunc(): + assert verifyConversion(DecBench, decFunc) == 0 + +## def testDecTaskFreeVar(): +## assert verifyConversion(DecBench, decTaskFreeVar) == 0 + +def testDecTask(): + assert verifyConversion(DecBench, decTask) == 0 + + +## def testDecRef(self): +## sim = self.bench(decRef) +## sim.run(quiet=1) + +## def testDec(self): +## sim = self.bench(dec) +## sim.run(quiet=1) + +## def testDecFunc(self): +## sim = self.bench(decFunc) +## sim.run(quiet=1) + +## signed inout in task doesn't work yet in Icarus +## def testDecTask(self): +## sim = self.bench(decTask) +## sim.run(quiet=1) + +## def testDecTaskFreeVar(self): +## sim = self.bench(decTaskFreeVar) +## sim.run(quiet=1) + + + + + + + + + + + + diff --git a/myhdl/test/toVHDL/test_fsm.py b/myhdl/test/toVHDL/test_fsm.py index 3a12c0a1..bfb41aac 100644 --- a/myhdl/test/toVHDL/test_fsm.py +++ b/myhdl/test/toVHDL/test_fsm.py @@ -198,8 +198,11 @@ def FSMBench(FramerCtrl, t_State): return framerctrl_inst, clkgen(), stimulus(), check() -verifyConversion(FSMBench, FramerCtrl, t_State_b) -verifyConversion(FSMBench, FramerCtrl_alt, t_State_b) +def testRef(): + assert verifyConversion(FSMBench, FramerCtrl, t_State_b) == 0 + +def testAlt(): + assert verifyConversion(FSMBench, FramerCtrl_alt, t_State_b) == 0 ## def testRef(self): ## for t_State in (t_State_b, t_State_oc, t_State_oh): diff --git a/myhdl/test/toVHDL/test_hec.py b/myhdl/test/toVHDL/test_hec.py index 25fd029c..d05d25e4 100644 --- a/myhdl/test/toVHDL/test_hec.py +++ b/myhdl/test/toVHDL/test_hec.py @@ -155,4 +155,5 @@ def HecBench(HecCalculator): ## sim = self.bench(HecCalculatorTask2) ## Simulation(sim).run() -verifyConversion(HecBench, HecCalculatorPlain) +def testPlain(): + assert verifyConversion(HecBench, HecCalculatorPlain) == 0 diff --git a/myhdl/test/toVHDL/test_inc.py b/myhdl/test/toVHDL/test_inc.py index 114cd3fe..2efbccea 100644 --- a/myhdl/test/toVHDL/test_inc.py +++ b/myhdl/test/toVHDL/test_inc.py @@ -104,7 +104,7 @@ def incTaskFreeVar(count, enable, clock, reset, n): return incTaskGen -def tb_inc(inc): +def IncBench(inc): NR_CYCLES = 201 @@ -140,10 +140,12 @@ def tb_inc(inc): return inc_inst, clockgen, monitor - -verifyConversion(tb_inc, incRef) -verifyConversion(tb_inc, inc) -verifyConversion(tb_inc, inc2) +def test_incReg(): + assert verifyConversion(IncBench, incRef) == 0 +def test_inc(): + assert verifyConversion(IncBench, inc) == 0 +def test_inc2(): + assert verifyConversion(IncBench, inc2) == 0 diff --git a/myhdl/test/toVHDL/test_ops.py b/myhdl/test/toVHDL/test_ops.py index d7443196..9a386cda 100644 --- a/myhdl/test/toVHDL/test_ops.py +++ b/myhdl/test/toVHDL/test_ops.py @@ -144,7 +144,14 @@ def binaryBench(m, n): ## self.assertEqual(RightShift, RightShift_v) ## self.assertEqual(Sub, Sub_v) ## self.assertEqual(Sum, Sum_v) - print Sum +## print Sub +## print Sum + print int(EQ) +## print NE +## print LT +## print GT +## print LE +## print GE ## self.assertEqual(EQ, EQ_v) ## self.assertEqual(NE, NE_v) ## self.assertEqual(LT, LT_v) @@ -157,8 +164,12 @@ def binaryBench(m, n): return binops, stimulus(), check() -for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): - verifyConversion(binaryBench, m, n) +def testBinary(): + for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): + yield checkBinary, m, n + +def checkBinary(m, n): + assert verifyConversion(binaryBench, m, n) == 0 diff --git a/myhdl/test/toVerilog/test_dec.py b/myhdl/test/toVerilog/test_dec.py index 54034ca1..32f9595e 100644 --- a/myhdl/test/toVerilog/test_dec.py +++ b/myhdl/test/toVerilog/test_dec.py @@ -203,7 +203,7 @@ class TestDec(TestCase): def testDecTaskFreeVar(self): sim = self.bench(decTaskFreeVar) - sim.run(quiet=1) + sim.run(quiet=0) if __name__ == '__main__': unittest.main()