mirror of
https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
test_dec and py.test
This commit is contained in:
jand
parent
3eccc04e51
commit
03665d67fa
@ -304,43 +304,55 @@ class _ConvertVisitor(_ToVerilogMixin):
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size = int(math.ceil(math.log(n+1,2))) + 1 # sign bit!
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self.write("%s'sd" % size)
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def writeDeclaration(self, obj, name, dir, endchar=";"):
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if dir: dir = dir + ' '
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if type(obj) is bool:
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self.write("%s%s: std_logic" % (dir, name))
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elif isinstance(obj, EnumItemType):
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self.write("%s%s: %s" % (dir, name, obj._type._name))
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elif isinstance(obj, int):
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if dir == "input ":
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self.write("input %s;" % name)
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self.writeline()
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self.write("variable %s: integer" % name)
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def writeDeclaration(self, obj, name, kind="", dir="", endchar=";", constr=True):
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if isinstance(obj, EnumItemType):
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tipe = obj._type._name
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elif isinstance(obj, _Ram):
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self.write("reg [%s-1:0] %s [0:%s-1]" % (obj.elObj._nrbits, name, obj.depth))
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elif hasattr(obj, '_nrbits'):
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s = "unsigned"
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if isinstance(obj, (intbv, Signal)):
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if obj._min is not None and obj._min < 0:
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s = "signed "
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if dir == "in ":
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self.write("%s: %s %s(%s-1 downto 0)" % (name, dir, s, obj._nrbits))
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else:
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self.write("%s%s: %s(%s-1 downto 0)" % (dir, name, s, obj._nrbits))
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tipe = "reg [%s-1:0] %s [0:%s-1]" % (obj.elObj._nrbits, name, obj.depth)
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else:
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raise AssertionError("var %s has unexpected type %s" % (name, type(obj)))
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# initialize regs
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# if dir == 'reg ' and not isinstance(obj, _Ram):
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# disable for cver
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if False:
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if isinstance(obj, EnumItemType):
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inival = obj._toVHDL()
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else:
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inival = int(obj)
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self.write(" = %s;" % inival)
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else:
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self.write(endchar)
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vhdlObj = inferVhdlObj(obj)
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tipe = vhdlObj.toStr(constr)
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if kind: kind += " "
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if dir: dir += " "
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self.write("%s%s: %s%s%s" % (kind, name, dir, tipe, endchar))
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## def writeDeclaration(self, obj, name, dir, endchar=";"):
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## if dir: dir = dir + ' '
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## if type(obj) is bool:
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## self.write("%s%s: std_logic" % (dir, name))
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## elif isinstance(obj, EnumItemType):
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## self.write("%s%s: %s" % (dir, name, obj._type._name))
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## elif isinstance(obj, int):
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## if dir == "input ":
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## self.write("input %s;" % name)
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## self.writeline()
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## self.write("variable %s: integer" % name)
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## elif isinstance(obj, _Ram):
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## self.write("reg [%s-1:0] %s [0:%s-1]" % (obj.elObj._nrbits, name, obj.depth))
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## elif hasattr(obj, '_nrbits'):
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## s = "unsigned"
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## if isinstance(obj, (intbv, Signal)):
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## if obj._min is not None and obj._min < 0:
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## s = "signed "
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## if dir == "in ":
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## self.write("%s: %s %s(%s-1 downto 0)" % (name, dir, s, obj._nrbits))
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## else:
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## self.write("%s%s: %s(%s-1 downto 0)" % (dir, name, s, obj._nrbits))
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## else:
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## raise AssertionError("var %s has unexpected type %s" % (name, type(obj)))
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## # initialize regs
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## # if dir == 'reg ' and not isinstance(obj, _Ram):
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## # disable for cver
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## if False:
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## if isinstance(obj, EnumItemType):
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## inival = obj._toVHDL()
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## else:
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## inival = int(obj)
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## self.write(" = %s;" % inival)
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## else:
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## self.write(endchar)
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def writeDeclarations(self):
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if self.ast.hasPrint:
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self.writeline()
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@ -349,7 +361,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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if isinstance(obj, _loopInt):
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continue # hack for loop vars
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self.writeline()
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self.writeDeclaration(obj, name, "variable")
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self.writeDeclaration(obj, name, kind="variable")
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def indent(self):
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self.ind += ' ' * 4
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@ -358,9 +370,9 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.ind = self.ind[:-4]
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def binaryOp(self, node, op=None):
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if isinstance(node.vhdlObj, vhdl_integer):
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node.left.vhdlObj = vhdl_integer()
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node.right.vhdlObj = vhdl_integer()
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if isinstance(node.vhdlObj, vhdl_int):
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node.left.vhdlObj = vhdl_int()
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node.right.vhdlObj = vhdl_int()
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context = None
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if node.signed:
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context = _context.SIGNED
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@ -451,6 +463,8 @@ class _ConvertVisitor(_ToVerilogMixin):
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def visitAssign(self, node, *args):
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assert len(node.nodes) == 1
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lhs = node.nodes[0]
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rhs = node.expr
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# shortcut for expansion of ROM in case statement
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if isinstance(node.expr, astNode.Subscript) and \
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isinstance(node.expr.expr.obj, _Rom):
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@ -473,22 +487,32 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.isSigAss = False
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else:
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self.write(' := ')
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self.write('"%s";' % bin(n, size))
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if isinstance(lhs.vhdlObj, vhdl_std_logic):
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self.write("'%s';" % n)
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elif isinstance(lhs.vhdlObj, vhdl_int):
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self.write("%s;" % n)
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else:
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self.write('"%s";' % bin(n, size))
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self.dedent()
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self.writeline()
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self.write("end case;")
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return
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# default behavior
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convOpen, convClose = "", ""
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lhs = node.nodes[0]
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rhs = node.expr
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if isinstance(lhs.vhdlObj, vhdl_unsigned):
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if isinstance(rhs.vhdlObj, vhdl_unsigned) and \
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(lhs.vhdlObj.size == rhs.vhdlObj.size):
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pass
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else:
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convOpen, convClose = "to_unsigned(", ", %s)" % lhs.vhdlObj.size
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rhs.vhdlObj = vhdl_integer()
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rhs.vhdlObj = vhdl_int()
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elif isinstance(lhs.vhdlObj, vhdl_signed):
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if isinstance(rhs.vhdlObj, vhdl_signed) and \
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(lhs.vhdlObj.size == rhs.vhdlObj.size):
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pass
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else:
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convOpen, convClose = "to_signed(", ", %s)" % lhs.vhdlObj.size
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rhs.vhdlObj = vhdl_int()
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elif isinstance(lhs.vhdlObj, vhdl_std_logic):
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rhs.vhdlObj = vhdl_std_logic()
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self.visit(node.nodes[0])
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@ -574,10 +598,10 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write(f.__name__)
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if node.args:
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self.write(opening)
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self.visit(node.args[0])
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self.visit(node.args[0], *args)
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for arg in node.args[1:]:
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self.write(sep)
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self.visit(arg)
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self.visit(arg, *args)
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self.write(closing)
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if hasattr(node, 'ast'):
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if node.ast.kind == _kind.TASK:
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@ -612,6 +636,8 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write("'%s'" % node.value)
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## elif target._type is intbv:
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## self.write('"%s"' % bin(node.value, len(target)))
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elif isinstance(node.vhdlObj, vhdl_boolean):
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self.write("%s" % bool(node.value))
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else:
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self.write(node.value)
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@ -797,20 +823,27 @@ class _ConvertVisitor(_ToVerilogMixin):
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addSignBit = isMixedExpr
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s = n
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obj = self.ast.vardict[n]
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if isinstance(obj, intbv) and isinstance(node.vhdlObj, vhdl_integer):
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if isinstance(obj, intbv) and isinstance(node.vhdlObj, vhdl_int):
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s = "to_integer(%s)" % n
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elif n in self.ast.argnames:
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assert n in self.ast.symdict
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addSignBit = isMixedExpr
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s = n
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obj = self.ast.symdict[n]
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vhdlObj = inferVhdlObj(obj)
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if isinstance(vhdlObj, vhdl_std_logic) and isinstance(node.vhdlObj, vhdl_boolean):
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s = "%s = '1'" % n
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else:
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s = n
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elif n in self.ast.symdict:
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obj = self.ast.symdict[n]
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#obj = node.obj
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if isinstance(obj, bool):
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s = "'%s'" % int(obj)
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elif isinstance(obj, (int, long)):
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if isinstance(node.vhdlObj, vhdl_integer):
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if isinstance(node.vhdlObj, vhdl_int):
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s = "%s" % int(obj)
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elif isinstance(node.vhdlObj, vhdl_std_logic):
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s = "'%s'" % int(obj)
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else:
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s = '"%s"' % bin(obj, node.vhdlObj.size)
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elif isinstance(obj, Signal):
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@ -827,7 +860,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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elif context == _context.BOOLEAN and \
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obj._type is bool:
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s = "%s = '1'" % str(obj)
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elif (obj._type is intbv) and isinstance(node.vhdlObj, vhdl_integer):
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elif (obj._type is intbv) and isinstance(node.vhdlObj, vhdl_int):
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s = "to_integer(%s)" % str(obj)
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else:
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addSignBit = isMixedExpr
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@ -846,11 +879,11 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj)))
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else:
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raise AssertionError("name ref: %s" % n)
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if addSignBit:
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self.write("$signed({1'b0, ")
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## if addSignBit:
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## self.write("$signed({1'b0, ")
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self.write(s)
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if addSignBit:
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self.write("})")
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## if addSignBit:
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## self.write("})")
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def visitPass(self, node, *args):
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self.write("null;")
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@ -1181,9 +1214,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
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self.returnLabel = _Label("RETURN")
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def writeOutputDeclaration(self):
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obj = self.ast.returnObj
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# self.writeDeclaration(obj, self.ast.name, dir='')
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self.write(inferVhdlObj(obj))
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self.write(self.ast.vhdlObj.toStr(constr=False))
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def writeInputDeclarations(self):
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endchar = ""
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@ -1192,7 +1223,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
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enchar = ";"
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obj = self.ast.symdict[name]
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self.writeline()
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self.writeDeclaration(obj, name, "in", endchar="")
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self.writeDeclaration(obj, name, dir="in", constr=False, endchar="")
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def visitFunction(self, node, *args):
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self.write("function %s(" % self.ast.name)
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@ -1201,8 +1232,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
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self.writeline()
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self.write(") return ")
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self.writeOutputDeclaration()
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self.writeline()
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self.write("is")
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self.write(" is")
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self.writeDeclarations()
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self.dedent()
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self.writeline()
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@ -1227,30 +1257,40 @@ class _ConvertTaskVisitor(_ConvertVisitor):
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self.returnLabel = _Label("RETURN")
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def writeInterfaceDeclarations(self):
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endchar = ""
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for name in self.ast.argnames:
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self.write(endchar)
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endchar = ";"
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obj = self.ast.symdict[name]
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output = name in self.ast.outputs
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input = name in self.ast.inputs
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inout = input and output
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dir = (inout and "inout") or (output and "output") or "input"
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dir = (inout and "inout") or (output and "out") or "in"
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self.writeline()
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self.writeDeclaration(obj, name, dir)
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self.writeDeclaration(obj, name, dir=dir, constr=False, endchar="")
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def visitFunction(self, node, *args):
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self.write("task %s;" % self.ast.name)
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self.indent()
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self.writeInterfaceDeclarations()
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self.write("procedure %s" % self.ast.name)
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if self.ast.argnames:
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self.write("(")
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self.indent()
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self.writeInterfaceDeclarations()
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self.write(") ")
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self.write("is")
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self.writeDeclarations()
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self.dedent()
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self.writeline()
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self.write("begin: %s" % self.returnLabel)
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self.write("begin")
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self.indent()
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print 'here'
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print node.code.nodes[0]
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t = node.code.nodes[0].tests[0][0]
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print t
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print t.vhdlObj
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self.visit(node.code)
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self.dedent()
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self.writeline()
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self.write("end")
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self.writeline()
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self.write("endtask")
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self.write("end procedure %s;" % self.ast.name)
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self.writeline(2)
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@ -1261,39 +1301,51 @@ class vhdl_type(object):
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class vhdl_std_logic(vhdl_type):
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def __init__(self, size=0):
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self.size = 1
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def __str__(self):
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def toStr(self, constr=True):
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return 'std_logic'
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class vhdl_boolean(vhdl_type):
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def __init__(self, size=0):
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self.size = 1
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def __str__(self):
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def toStr(self, constr=True):
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return 'boolean'
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class vhdl_unsigned(vhdl_type):
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def __str__(self):
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return "unsigned(%s downto 0)" % (self.size-1)
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def toStr(self, constr=True):
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if constr:
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return "unsigned(%s downto 0)" % (self.size-1)
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else:
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return "unsigned"
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class vhdl_signed(vhdl_type):
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def __str__(self):
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return "signed(%s downto 0)" % (self.size-1)
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def toStr(self, constr=True):
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if constr:
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return "signed(%s downto 0)" % (self.size-1)
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else:
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return "signed"
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class vhdl_integer(vhdl_type):
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def __str__(self):
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class vhdl_int(vhdl_type):
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def toStr(self, constr=True):
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return "integer"
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class _loopInt(int):
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pass
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def maxType(t1, t2):
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if t1 is vhdl_signed or t2 is vhdl_signed:
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return vhdl_signed
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elif t1 is vhdl_unsigned or t2 is vhdl_unsigned:
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return vhdl_unsigned
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elif t1 is vhdl_std_logic or t2 is vhdl_std_logic:
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return vhdl_std_logic
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elif t1 is vhdl_integer or t2 is vhdl_integer:
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return vhdl_integer
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def maxType(o1, o2):
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s1 = s2 = 0
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if isinstance(o1, vhdl_type):
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s1 = o1.size
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if isinstance(o2, vhdl_type):
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s2 = o2.size
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s = max(s1, s2)
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if isinstance(o1, vhdl_signed) or isinstance(o2, vhdl_signed):
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return vhdl_signed(s)
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elif isinstance(o1, vhdl_unsigned) or isinstance(o2, vhdl_unsigned):
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return vhdl_unsigned(s)
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elif isinstance(o1, vhdl_std_logic) or isinstance(o2, vhdl_std_logic):
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return vhdl_std_logic()
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elif isinstance(o1, vhdl_int) or isinstance(o2, vhdl_int):
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return vhdl_int()
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else:
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return None
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@ -1309,7 +1361,7 @@ def inferVhdlObj(obj):
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isinstance(obj, bool):
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vhdlObj = vhdl_std_logic()
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elif isinstance(obj, (int, long)):
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vhdlObj = vhdl_integer()
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vhdlObj = vhdl_int()
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return vhdlObj
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@ -1326,34 +1378,32 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
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fn = node.node
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assert isinstance(fn, astNode.Name)
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f = self.getObj(fn)
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if f is intbv:
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return
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node.vhdlObj = inferVhdlObj(node.obj)
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self.visitChildNodes(node)
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if f is concat:
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s = 0
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for a in node.args:
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s += a.vhdlObj.size
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node.vhdlObj = vhdl_unsigned(s)
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elif f is intbv:
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node.vhdlObj = vhdl_int()
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elif f is len:
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node.vhdlObj = vhdl_integer()
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node.vhdlObj = vhdl_int()
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elif hasattr(node, 'ast'):
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v = _AnnotateTypesVisitor(node.ast)
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compiler.walk(node.ast, v)
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vhdlObj = inferVhdlObj(node.ast.returnObj)
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node.vhdlObj = self.ast.vhdlObj = vhdlObj
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node.vhdlObj = node.ast.vhdlObj = inferVhdlObj(node.ast.returnObj)
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def visitCompare(self, node):
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node.vhdlObj = vhdl_boolean()
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self.visitChildNodes(node)
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expr = node.expr
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op, code = node.ops[0]
|
||||
s = max(expr.vhdlObj.size, code.vhdlObj.size)
|
||||
t = maxType(type(expr.vhdlObj), type(code.vhdlObj))
|
||||
expr.vhdlObj = t(s)
|
||||
code.vhdlObj = t(s)
|
||||
o = maxType(expr.vhdlObj, code.vhdlObj)
|
||||
expr.vhdlObj = code.vhdlObj = o
|
||||
|
||||
def visitConst(self, node):
|
||||
node.vhdlObj = vhdl_integer()
|
||||
node.vhdlObj = vhdl_int()
|
||||
|
||||
def visitFor(self, node):
|
||||
self.visitChildNodes(node)
|
||||
@ -1361,6 +1411,10 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
|
||||
# make it possible to detect loop variable
|
||||
self.ast.vardict[var] = _loopInt()
|
||||
|
||||
def visitGetattr(self, node):
|
||||
self.visitChildNodes(node)
|
||||
node.vhdlObj = None
|
||||
|
||||
def visitName(self, node):
|
||||
node.vhdlObj = inferVhdlObj(node.obj)
|
||||
|
||||
@ -1374,25 +1428,25 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
|
||||
self.visit(node.right)
|
||||
r = node.right.vhdlObj
|
||||
l = node.left.vhdlObj
|
||||
if isinstance(r, vhdl_signed) and isinstance(l, vhdl_signed):
|
||||
if isinstance(r, vhdl_int) and isinstance(l, vhdl_int):
|
||||
node.vhdlObj = vhdl_int()
|
||||
elif isinstance(r, (vhdl_signed, vhdl_int)) and isinstance(l, (vhdl_signed, vhdl_int)):
|
||||
node.vhdlObj = vhdl_signed(max(l.size, r.size))
|
||||
elif isinstance(r, vhdl_unsigned) and isinstance(l, vhdl_unsigned):
|
||||
elif isinstance(r, (vhdl_unsigned, vhdl_int)) and isinstance(l, (vhdl_unsigned, vhdl_int)):
|
||||
node.vhdlObj = vhdl_unsigned(max(l.size, r.size))
|
||||
else:
|
||||
node.vhdlObj = vhdl_integer()
|
||||
node.vhdlObj = vhdl_int()
|
||||
|
||||
visitAdd = visitSub = visitMod = binaryOp
|
||||
|
||||
def multiBitOp(self, node):
|
||||
self.visitChildNodes(node)
|
||||
t = vhdl_std_logic
|
||||
s = 0
|
||||
o = None
|
||||
for n in node.nodes:
|
||||
s = max(s, n.vhdlObj.size)
|
||||
t = maxType(t, type(n.vhdlObj))
|
||||
o = maxType(o, n.vhdlObj)
|
||||
for n in node.nodes:
|
||||
n.vhdlObj = t(s)
|
||||
node.vhdlObj = t(s)
|
||||
n.vhdlObj = o
|
||||
node.vhdlObj = o
|
||||
|
||||
def multiBoolOp(self, node):
|
||||
self.visitChildNodes(node)
|
||||
@ -1402,8 +1456,13 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
|
||||
visitBitand = visitBitor = visitBitxor = multiBitOp
|
||||
|
||||
def visitNot(self, node):
|
||||
node.vhdlObj = None
|
||||
self.visit(node.expr)
|
||||
node.vhdlObj = vhdl_boolean()
|
||||
|
||||
def visitIf(self, node):
|
||||
self.visitChildNodes(node)
|
||||
for test, suite in node.tests:
|
||||
test.vhdlObj = vhdl_boolean()
|
||||
|
||||
def visitSlice(self, node):
|
||||
self.visitChildNodes(node)
|
||||
@ -1423,6 +1482,17 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
|
||||
self.visitChildNodes(node)
|
||||
node.vhdlObj = vhdl_std_logic()
|
||||
|
||||
def unaryOp(self, node):
|
||||
self.visit(node.expr)
|
||||
node.vhdlObj = node.expr.vhdlObj
|
||||
|
||||
visitUnaryAdd = visitUnarySub = unaryOp
|
||||
|
||||
def visitWhile(self, node):
|
||||
self.visitChildNodes(node)
|
||||
node.test.vhdlObj = vhdl_boolean()
|
||||
|
||||
|
||||
|
||||
|
||||
def _annotateTypes(genlist):
|
||||
|
||||
@ -131,7 +131,7 @@ def _analyzeGens(top, absnames):
|
||||
s = re.sub(r"@.*", "", s)
|
||||
s = s.lstrip()
|
||||
ast = compiler.parse(s)
|
||||
print ast
|
||||
#print ast
|
||||
ast.sourcefile = inspect.getsourcefile(f)
|
||||
ast.lineoffset = inspect.getsourcelines(f)[1]-1
|
||||
ast.symdict = f.func_globals.copy()
|
||||
@ -159,7 +159,7 @@ def _analyzeGens(top, absnames):
|
||||
s = re.sub(r"@.*", "", s)
|
||||
s = s.lstrip()
|
||||
ast = compiler.parse(s)
|
||||
print ast
|
||||
#print ast
|
||||
ast.sourcefile = inspect.getsourcefile(f)
|
||||
ast.lineoffset = inspect.getsourcelines(f)[1]-1
|
||||
ast.symdict = f.f_globals.copy()
|
||||
@ -518,6 +518,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
|
||||
compiler.walk(ast, v)
|
||||
v = _AnalyzeFuncVisitor(ast, node.args)
|
||||
compiler.walk(ast, v)
|
||||
node.obj = ast.returnObj
|
||||
node.ast = ast
|
||||
for i, arg in enumerate(node.args):
|
||||
if isinstance(arg, astNode.Keyword):
|
||||
@ -786,6 +787,13 @@ class _AnalyzeVisitor(_ToVerilogMixin):
|
||||
senslist = [n.obj]
|
||||
node.senslist = senslist
|
||||
|
||||
## def visitModule(self, node, *args):
|
||||
## self.visit(node.node)
|
||||
## for n in self.ast.inputs:
|
||||
## s = self.ast.sigdict[n]
|
||||
## s._read = True
|
||||
|
||||
|
||||
|
||||
class _AnalyzeBlockVisitor(_AnalyzeVisitor):
|
||||
|
||||
|
||||
@ -71,7 +71,8 @@ def bin2grayBench(width, bin2gray):
|
||||
## sim = self.bench(width=8, bin2gray=bin2gray2)
|
||||
## Simulation(sim).run()
|
||||
|
||||
|
||||
verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray)
|
||||
verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray2)
|
||||
def test1():
|
||||
assert verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray) == 0
|
||||
def test2():
|
||||
assert verifyConversion(bin2grayBench, width=8, bin2gray=bin2gray2) == 0
|
||||
|
||||
|
||||
220
myhdl/test/toVHDL/test_dec.py
Normal file
220
myhdl/test/toVHDL/test_dec.py
Normal file
@ -0,0 +1,220 @@
|
||||
import os
|
||||
path = os.path
|
||||
import random
|
||||
from random import randrange
|
||||
random.seed(2)
|
||||
|
||||
from myhdl import *
|
||||
from myhdl.test import verifyConversion
|
||||
|
||||
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
|
||||
|
||||
|
||||
def decRef(count, enable, clock, reset, n):
|
||||
""" Decrementer with enable.
|
||||
|
||||
count -- output
|
||||
enable -- control input, decrement when 1
|
||||
clock -- clock input
|
||||
reset -- asynchronous reset input
|
||||
n -- counter max value
|
||||
"""
|
||||
while 1:
|
||||
yield clock.posedge, reset.negedge
|
||||
if reset == ACTIVE_LOW:
|
||||
count.next = 0
|
||||
else:
|
||||
if enable:
|
||||
if count == -n:
|
||||
count.next = n-1
|
||||
else:
|
||||
count.next = count - 1
|
||||
|
||||
|
||||
def dec(count, enable, clock, reset, n):
|
||||
""" Decrementer with enable.
|
||||
|
||||
count -- output
|
||||
enable -- control input, decrement when 1
|
||||
clock -- clock input
|
||||
reset -- asynchronous reset input
|
||||
n -- counter max value
|
||||
"""
|
||||
def decProcess():
|
||||
while 1:
|
||||
yield clock.posedge, reset.negedge
|
||||
if reset == ACTIVE_LOW:
|
||||
count.next = 0
|
||||
else:
|
||||
if enable:
|
||||
if count == -n:
|
||||
count.next = n-1
|
||||
else:
|
||||
count.next = count - 1
|
||||
return decProcess()
|
||||
|
||||
|
||||
def decFunc(count, enable, clock, reset, n):
|
||||
|
||||
def decFuncFunc(cnt):
|
||||
count_next = intbv(0, min=-n, max=n)
|
||||
if cnt == -n:
|
||||
count_next[:] = n-1
|
||||
else:
|
||||
count_next[:] = cnt - 1
|
||||
return count_next
|
||||
|
||||
@always(clock.posedge, reset.negedge)
|
||||
def decFuncGen():
|
||||
if reset == ACTIVE_LOW:
|
||||
count.next = 0
|
||||
else:
|
||||
if enable:
|
||||
count.next = decFuncFunc(count)
|
||||
|
||||
return decFuncGen
|
||||
|
||||
|
||||
def decTask(count, enable, clock, reset, n):
|
||||
|
||||
def decTaskFunc(cnt, enable, reset, n):
|
||||
if enable:
|
||||
if cnt == -n:
|
||||
cnt[:] = n-1
|
||||
else:
|
||||
cnt[:] = cnt - 1
|
||||
|
||||
def decTaskGen():
|
||||
cnt = intbv(0, min=-n, max=n)
|
||||
while 1:
|
||||
yield clock.posedge, reset.negedge
|
||||
if reset == ACTIVE_LOW:
|
||||
cnt[:] = 0
|
||||
count.next = 0
|
||||
else:
|
||||
# print count
|
||||
decTaskFunc(cnt, enable, reset, n)
|
||||
count.next = cnt
|
||||
|
||||
return decTaskGen()
|
||||
|
||||
|
||||
def decTaskFreeVar(count, enable, clock, reset, n):
|
||||
|
||||
def decTaskFunc():
|
||||
if enable:
|
||||
if count == -n:
|
||||
count.next = n-1
|
||||
else:
|
||||
count.next = count - 1
|
||||
|
||||
def decTaskGen():
|
||||
while 1:
|
||||
yield clock.posedge, reset.negedge
|
||||
if reset == ACTIVE_LOW:
|
||||
count.next = 0
|
||||
else:
|
||||
# print count
|
||||
decTaskFunc()
|
||||
|
||||
return decTaskGen()
|
||||
|
||||
|
||||
|
||||
def DecBench(dec):
|
||||
|
||||
m = 8
|
||||
n = 2 ** (m-1)
|
||||
|
||||
count = Signal(intbv(0, min=-n, max=n))
|
||||
count_v = Signal(intbv(0, min=-n, max=n))
|
||||
enable = Signal(bool(0))
|
||||
clock, reset = [Signal(bool(1)) for i in range(2)]
|
||||
|
||||
@instance
|
||||
def clockGen():
|
||||
yield delay(10)
|
||||
clock.next = 0
|
||||
while 1:
|
||||
yield delay(10)
|
||||
clock.next = not clock
|
||||
|
||||
enables = tuple([min(1, randrange(5)) for i in range(1000)])
|
||||
@instance
|
||||
def stimulus():
|
||||
reset.next = INACTIVE_HIGH
|
||||
yield clock.negedge
|
||||
reset.next = ACTIVE_LOW
|
||||
yield clock.negedge
|
||||
reset.next = INACTIVE_HIGH
|
||||
for i in range(1000):
|
||||
enable.next = 1
|
||||
yield clock.negedge
|
||||
for i in range(len(enables)):
|
||||
enable.next = enables[i]
|
||||
yield clock.negedge
|
||||
raise StopSimulation
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield reset.posedge
|
||||
print count
|
||||
while 1:
|
||||
yield clock.posedge
|
||||
yield delay(1)
|
||||
print count
|
||||
|
||||
dec_inst = dec(count, enable, clock, reset, n=n)
|
||||
|
||||
return dec_inst, clockGen, stimulus, check
|
||||
|
||||
|
||||
|
||||
def testDecRef():
|
||||
assert verifyConversion(DecBench, decRef) == 0
|
||||
|
||||
def testDec():
|
||||
assert verifyConversion(DecBench, dec) == 0
|
||||
|
||||
def testDecFunc():
|
||||
assert verifyConversion(DecBench, decFunc) == 0
|
||||
|
||||
## def testDecTaskFreeVar():
|
||||
## assert verifyConversion(DecBench, decTaskFreeVar) == 0
|
||||
|
||||
def testDecTask():
|
||||
assert verifyConversion(DecBench, decTask) == 0
|
||||
|
||||
|
||||
## def testDecRef(self):
|
||||
## sim = self.bench(decRef)
|
||||
## sim.run(quiet=1)
|
||||
|
||||
## def testDec(self):
|
||||
## sim = self.bench(dec)
|
||||
## sim.run(quiet=1)
|
||||
|
||||
## def testDecFunc(self):
|
||||
## sim = self.bench(decFunc)
|
||||
## sim.run(quiet=1)
|
||||
|
||||
## signed inout in task doesn't work yet in Icarus
|
||||
## def testDecTask(self):
|
||||
## sim = self.bench(decTask)
|
||||
## sim.run(quiet=1)
|
||||
|
||||
## def testDecTaskFreeVar(self):
|
||||
## sim = self.bench(decTaskFreeVar)
|
||||
## sim.run(quiet=1)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -198,8 +198,11 @@ def FSMBench(FramerCtrl, t_State):
|
||||
return framerctrl_inst, clkgen(), stimulus(), check()
|
||||
|
||||
|
||||
verifyConversion(FSMBench, FramerCtrl, t_State_b)
|
||||
verifyConversion(FSMBench, FramerCtrl_alt, t_State_b)
|
||||
def testRef():
|
||||
assert verifyConversion(FSMBench, FramerCtrl, t_State_b) == 0
|
||||
|
||||
def testAlt():
|
||||
assert verifyConversion(FSMBench, FramerCtrl_alt, t_State_b) == 0
|
||||
|
||||
## def testRef(self):
|
||||
## for t_State in (t_State_b, t_State_oc, t_State_oh):
|
||||
|
||||
@ -155,4 +155,5 @@ def HecBench(HecCalculator):
|
||||
## sim = self.bench(HecCalculatorTask2)
|
||||
## Simulation(sim).run()
|
||||
|
||||
verifyConversion(HecBench, HecCalculatorPlain)
|
||||
def testPlain():
|
||||
assert verifyConversion(HecBench, HecCalculatorPlain) == 0
|
||||
|
||||
@ -104,7 +104,7 @@ def incTaskFreeVar(count, enable, clock, reset, n):
|
||||
return incTaskGen
|
||||
|
||||
|
||||
def tb_inc(inc):
|
||||
def IncBench(inc):
|
||||
|
||||
NR_CYCLES = 201
|
||||
|
||||
@ -140,10 +140,12 @@ def tb_inc(inc):
|
||||
return inc_inst, clockgen, monitor
|
||||
|
||||
|
||||
|
||||
verifyConversion(tb_inc, incRef)
|
||||
verifyConversion(tb_inc, inc)
|
||||
verifyConversion(tb_inc, inc2)
|
||||
def test_incReg():
|
||||
assert verifyConversion(IncBench, incRef) == 0
|
||||
def test_inc():
|
||||
assert verifyConversion(IncBench, inc) == 0
|
||||
def test_inc2():
|
||||
assert verifyConversion(IncBench, inc2) == 0
|
||||
|
||||
|
||||
|
||||
|
||||
@ -144,7 +144,14 @@ def binaryBench(m, n):
|
||||
## self.assertEqual(RightShift, RightShift_v)
|
||||
## self.assertEqual(Sub, Sub_v)
|
||||
## self.assertEqual(Sum, Sum_v)
|
||||
print Sum
|
||||
## print Sub
|
||||
## print Sum
|
||||
print int(EQ)
|
||||
## print NE
|
||||
## print LT
|
||||
## print GT
|
||||
## print LE
|
||||
## print GE
|
||||
## self.assertEqual(EQ, EQ_v)
|
||||
## self.assertEqual(NE, NE_v)
|
||||
## self.assertEqual(LT, LT_v)
|
||||
@ -157,8 +164,12 @@ def binaryBench(m, n):
|
||||
return binops, stimulus(), check()
|
||||
|
||||
|
||||
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
|
||||
verifyConversion(binaryBench, m, n)
|
||||
def testBinary():
|
||||
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
|
||||
yield checkBinary, m, n
|
||||
|
||||
def checkBinary(m, n):
|
||||
assert verifyConversion(binaryBench, m, n) == 0
|
||||
|
||||
|
||||
|
||||
|
||||
@ -203,7 +203,7 @@ class TestDec(TestCase):
|
||||
|
||||
def testDecTaskFreeVar(self):
|
||||
sim = self.bench(decTaskFreeVar)
|
||||
sim.run(quiet=1)
|
||||
sim.run(quiet=0)
|
||||
|
||||
if __name__ == '__main__':
|
||||
unittest.main()
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user