Fix docstring for ModuleInstance; migrate example

example/manual/FramerCtrl.v

@@ -1,6 +1,6 @@
 // File: FramerCtrl.v
-// Generated by MyHDL 0.8dev
-// Date: Fri Dec 21 15:02:39 2012
+// Generated by MyHDL 1.0dev
+// Date: Mon Feb 15 21:03:52 2016
 
 
 `timescale 1ns/10ps
@@ -35,7 +35,7 @@ reg [7:0] index;
 
 
 always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM
-    if ((reset_n == 0)) begin
+    if ((reset_n == 1'b0)) begin
         SOF <= 0;
         index <= 0;
         state <= 3'b001;
@@ -66,7 +66,7 @@ always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM
                         state <= 3'b001;
                     end
                 end
-                SOF <= (index == (8 - 1));
+                SOF <= ($signed({1'b0, index}) == (8 - 1));
             end
             default: begin
                 $finish;

example/manual/FramerCtrl.vhd

@@ -1,11 +1,13 @@
 -- File: FramerCtrl.vhd
--- Generated by MyHDL 0.8dev
--- Date: Fri Dec 21 15:02:39 2012
+-- Generated by MyHDL 1.0dev
+-- Date: Mon Feb 15 21:03:52 2016
 
 
 
 package pck_FramerCtrl is
 
+attribute enum_encoding: string;
+
     type t_enum_t_State_1 is (
     SEARCH,
     CONFIRM,
@@ -20,7 +22,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use std.textio.all;
 
-use work.pck_myhdl_08.all;
+use work.pck_myhdl_10.all;
 
 use work.pck_FramerCtrl.all;
 
@@ -43,6 +45,8 @@ end entity FramerCtrl;
 
 architecture MyHDL of FramerCtrl is
 
+
+
 signal index: unsigned(7 downto 0);
 
 begin
@@ -50,18 +54,19 @@ begin
 
 
 
+
 FRAMERCTRL_FSM: process (clk, reset_n) is
 begin
     if (reset_n = '0') then
         SOF <= '0';
-        index <= "00000000";
+        index <= to_unsigned(0, 8);
         state <= SEARCH;
     elsif rising_edge(clk) then
         index <= ((index + 1) mod 8);
         SOF <= '0';
         case state is
             when SEARCH =>
-                index <= "00000001";
+                index <= to_unsigned(1, 8);
                 if bool(syncFlag) then
                     state <= CONFIRM;
                 end if;

example/manual/fsm3.py

@@ -9,6 +9,7 @@ ACTIVE_LOW = bool(0)
 FRAME_SIZE = 8
 t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
 
+@module
 def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
     
     """ Framing control FSM.
@@ -62,8 +63,8 @@ def main():
     reset_n = Signal(bool(1))
     state = Signal(t_State.SEARCH)
 
-    toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n)
-    toVHDL(FramerCtrl, SOF, state, syncFlag, clk, reset_n)
+    toVerilog(FramerCtrl(SOF, state, syncFlag, clk, reset_n))
+    toVHDL(FramerCtrl(SOF, state, syncFlag, clk, reset_n))
 
 
 if __name__ == '__main__':

myhdl/_module.py

@@ -54,10 +54,10 @@ def _getCallInfo():
     3: the function that defines instances
     4: the caller of the module function, e.g. a ModuleInstance.
 
-    There is a complication when the decorator is used in on a method.
+    There is a complication when the decorator is used on a method.
     In this case, it is used as a descriptor, and there is an additional
     stack level due to the __get__ method. The current hack is to check
-    whether we are still in this Python module at level 3, and increment
+    whether we are still in this module at level 3, and increment
     all the subsequent levels.
     """
 
@@ -117,6 +117,7 @@ class _ModuleInstance(object):
         self.args = args
         self.kwargs = kwargs
         self.mod = mod
+        self.__doc__ = mod.modfunc.__doc__
         callinfo = _getCallInfo()
         self.callinfo = callinfo
         self.modctxt = callinfo.modctxt