index

doc/manual/background.tex

@@ -19,9 +19,8 @@ or VHDL is helpful.
 
 \section{A small tutorial on generators \label{tutorial}}
 
-Generators are a recent feature in Python. They were introduced in
+Generators are a recent Python feature, introduced in
-Python 2.2, which is the most recent stable version at the time of
+Python 2.2. Therefore, there isn't a lot of tutorial material
-this writing. Therefore, there isn't a lot of tutorial material
 available yet. Because generators are the key concept in
 \myhdl{}, I include a small tutorial here.
 
@@ -105,7 +104,9 @@ The use of generators to model concurrency is the first key concept in
 \myhdl{}. The second key concept is a related one: in \myhdl{}, the
 yielded values are used to define the condition upon which the
 generator should resume. In other words, \keyword{yield}
-statements work as generalized sensitivity lists. 
+statements work as generalized 
+    \index{sensitivity list}%
+sensitivity lists. 
 
 If you want to know more about generators, consult the on-line Python
 documentation, e.g. at \url{http://www.python.org/doc/2.2.2/whatsnew}. 

doc/manual/informal.tex

@@ -52,8 +52,11 @@ there is a \code{delay} clause, that specifies the required delay.
 
 To make sure that the generator runs ``forever'', we wrap its behavior
 in a \code{while 1} loop. This is a standard Python idiom, and it is
-the \myhdl\ equivalent of the implicit looping behavior of a Verilog
+the \myhdl\ equivalent of the implicit looping behavior of a 
-\keyword{always} block and a VHDL \keyword{process}.
+    \index{Verilog!always block}% 
+Verilog \keyword{always} block
+    \index{VHDL!process}%
+and a VHDL \keyword{process}.
 
 In \myhdl{}, the basic simulation objects are generators. Generators
 are created by calling generator functions. For example, variable
@@ -95,9 +98,11 @@ The \code{clk} signal is constructed with an initial value
 \code{0}. In the clock generator function \code{clkGen}, it is
 continuously assigned a new value after a certain delay. In \myhdl{},
 the new value of a signal is specified by assigning to its
-\code{next} attribute. This is the \myhdl\ equivalent of the VHDL signal
+\code{next} attribute. This is the \myhdl\ equivalent of 
-assignment \index{VHDL!signal assignment} and the Verilog non-blocking
+    \index{VHDL!signal assignment}%
-assignment \index{Verilog!non-blocking assignment}.
+the VHDL signal assignment and the 
+    \index{Verilog!non-blocking assignment}%
+Verilog non-blocking assignment.
 
 The \code{sayHello} generator function is modified to wait for a
 rising edge of the clock instead of a delay:
@@ -240,7 +245,7 @@ def bin2gray(B, G, width):
     G -- output intbv signal, Gray encoded
     width -- bit width
 
-    """
+    """xc
     while 1:
         yield B
         for i in range(width):
@@ -253,7 +258,9 @@ Python practice for structured documentation of code. Moreover, we
 use a third form of the \keyword{yield} statement:
 \samp{yield \var{signal}}. This specifies that the generator should
 resume whenever \var{signal} changes value. This is typically used to
-describe combinatorial logic.
+describe 
+    \index{combinatorial logic}%
+combinatorial logic.
 Finally, the code contains bit indexing operations and an exclusive-or
 operator as required for a Gray encoder. By convention, the lsb of an
 \class{intbv} object has index~\code{0}.
@@ -455,6 +462,7 @@ Until now, the \code{yield} statements had a single clause. However,
 they can have multiple clauses as well. In that case, the calling
 generator is triggered as soon as the condition corresponding to one
 of the clauses is satisfied. This corresponds to the functionality of
+    \index{sensitivity list}%
 sensitivity lists in Verilog and VHDL.
 
 For example, suppose we want to design an UART receive procedure with
@@ -698,5 +706,3 @@ rewrite performance critical modules in C if necessary.
 
 
 
-
-

doc/manual/modeling.tex

@@ -122,6 +122,7 @@ The present section describes how \myhdl\ supports RTL style modeling
 as is typically used for synthesizable models in Verilog or VHDL. 
 
 \subsection{Combinatorial logic \label{model-comb}}
+\index{combinatorial logic|(}
 
 \subsubsection{Template \label{model-comb-templ}}
  
@@ -239,9 +240,11 @@ z a b sel
 3 3 5 1
 StopSimulation: No more events
 \end{verbatim}
+\index{combinatorial logic|)}
 
 
 \subsection{Sequential logic \label{model-seq}}
+\index{sequential logic|(}
 
 \subsubsection{Template \label{model-seq-templ}}
 Sequential RTL models are sensitive to a clock edge. In addition, they
@@ -340,6 +343,7 @@ enable  count
    1      2
 StopSimulation
 \end{verbatim}
+\index{sequential logic|)}
 
 
 \subsection{Finite State Machine modeling \label{model-fsm}}

doc/manual/reference.tex

@@ -103,7 +103,9 @@ maximum.
 
 \myhdl\ generators are standard Python generators with specialized
 \keyword{yield} statements. In hardware description languages, the equivalent
-statements are called \emph{sensitivity lists}. The general format
+statements are called 
+    \index{sensitivity list}%
+\emph{sensitivity lists}. The general format
 of \keyword{yield} statements in in \myhdl\ generators is:
 
 \hspace{\leftmargin}\keyword{yield} \var{clause \optional{, clause ...}}