spell check

doc/cosimulation.tex

@@ -251,7 +251,7 @@ applications with the Verilog PLI can testify, the
 restrictions in a particular simulator, and the 
 differences over various simulators, can be quite 
 frustrating. Moreover, full generality may require
-a disproportiate amount of development work compared
+a disproportionate amount of development work compared
 to a slightly less general solution that may
 be sufficient for the target application.
 
@@ -282,20 +282,20 @@ isn't.
 designs can be written in Python.
 Let's consider the nature of the target HDL designs. For high-level,
 behavioral models that are not intended for implementation, it should
-come as no surprize that I would recommend to write them in \myhdl\
+come as no surprise that I would recommend to write them in \myhdl\
 directly; that is exactly the target of the \myhdl\ effort. Likewise,
 gate level designs with annotated timing are not the target
 application: static timing analysis is a much better verification
 method for such designs.
 
-Rather, the targetted HDL designs are naturally models that are
+Rather, the targeted HDL designs are naturally models that are
 intended for implementation.  Most likely, this will be through
 synthesis. As time delays are meaningless in synthesizable code, the
 restriction is compatible with the target application.
 
 \subsection{Race sensitivity issues}
 
-In a typical RTL code, some events cause other events to occur in the
+In a typical TTL code, some events cause other events to occur in the
 same time step. For example, when a clock signal triggers some signals
 may change in the same time step. For race-free operation, an HDL
 must differentiate between such events within a time step. This is done