From 09309a2c7adc0e9c6940bc36643bebfad1207abf Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Tue, 12 Jul 2005 10:23:45 +0000
Subject: [PATCH] fixed always_comb singleton senslist handling make sure
 signal name equals port name when converting

---
 myhdl/_Simulation.py                         | 6 +++---
 myhdl/_always_comb.py                        | 4 ++--
 myhdl/_toVerilog/_analyze.py                 | 1 +
 myhdl/_toVerilog/_convert.py                 | 6 +++---
 myhdl/test/toVerilog/test_RandomScrambler.py | 3 +++
 5 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py
index 80efa04e..bd2b57e1 100644
--- a/myhdl/_Simulation.py
+++ b/myhdl/_Simulation.py
@@ -207,10 +207,10 @@ def _checkArgs(arglist):
         if isinstance(arg, GeneratorType):
             waiters.append(_inferWaiter(arg))
         elif isinstance(arg, _AlwaysComb):
-            if isinstance(arg.senslist, tuple):
-                waiters.append(_SignalTupleWaiter(arg.gen))
-            else:
+            if len(arg.senslist) == 1:
                 waiters.append(_SignalWaiter(arg.gen))
+            else:
+                waiters.append(_SignalTupleWaiter(arg.gen))
         elif isinstance(arg, Cosimulation):
             if cosim is not None:
                 raise SimulationError(_error.MultipleCosim)
diff --git a/myhdl/_always_comb.py b/myhdl/_always_comb.py
index 55990676..1da9ede6 100644
--- a/myhdl/_always_comb.py
+++ b/myhdl/_always_comb.py
@@ -168,12 +168,12 @@ class _AlwaysComb(object):
         self.inputs = v.inputs
         self.outputs = v.outputs
         self.senslist = tuple([self.sigdict[n] for n in self.inputs])
-        if len(self.senslist) == 1:
-            self.senslist = self.senslist[0]
         self.gen = self.genfunc()
 
     def genfunc(self):
         senslist = self.senslist
+        if len(senslist) == 1:
+            senslist = senslist[0]
         func = self.func
         while 1:
             func()
diff --git a/myhdl/_toVerilog/_analyze.py b/myhdl/_toVerilog/_analyze.py
index aa927009..72e73686 100644
--- a/myhdl/_toVerilog/_analyze.py
+++ b/myhdl/_toVerilog/_analyze.py
@@ -62,6 +62,7 @@ def _analyzeSigs(hierarchy):
             prefixes.append(name)
         else:
             prefixes = prefixes[:curlevel]
+        # print sigdict
         for n, s in sigdict.items():
             if s._name is None:
                 if len(prefixes) > 1:
diff --git a/myhdl/_toVerilog/_convert.py b/myhdl/_toVerilog/_convert.py
index f2508a91..6983d532 100644
--- a/myhdl/_toVerilog/_convert.py
+++ b/myhdl/_toVerilog/_convert.py
@@ -116,10 +116,10 @@ def _writeModuleHeader(f, intf):
     print >> f
     for portname in intf.argnames:
         s = intf.argdict[portname]
-        if s._name != portname:
-            print s._name
-            print portname
+        if s._name is None:
             raise ToVerilogError(_error.ShadowingSignal, portname)
+        # make sure signal name is equal to its port name
+        s._name = portname
         r = _getRangeString(s)
         if s._driven:
             print >> f, "output %s%s;" % (r, portname)
diff --git a/myhdl/test/toVerilog/test_RandomScrambler.py b/myhdl/test/toVerilog/test_RandomScrambler.py
index 185b0b87..a2be21b5 100644
--- a/myhdl/test/toVerilog/test_RandomScrambler.py
+++ b/myhdl/test/toVerilog/test_RandomScrambler.py
@@ -74,12 +74,14 @@ v7, v6, v5, v4, v3, v2, v1, v0 = [Signal(bool()) for i in range(N)]
 objfile = "rs.o"         
 analyze_cmd = "iverilog -o %s rs.v tb_rs.v" % objfile
 simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
+cmd = "cver -q +loadvpi=../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap rs.v tb_rs.v"
       
  
 def RandomScrambler_v(o7, o6, o5, o4, o3, o2, o1, o0,
                       i7, i6, i5, i4, i3, i2, i1, i0):
     if path.exists(objfile):
         os.remove(objfile)
+    # return Cosimulation(cmd, **locals())
     os.system(analyze_cmd)
     return Cosimulation(simulate_cmd, **locals())
 
@@ -91,6 +93,7 @@ class TestRandomScrambler(TestCase):
         output = intbv()
         output_v = intbv()
         for i in range(100):
+        # while 1:
             input[:] = randrange(M)
             i7.next = input[7]
             i6.next  = input[6]