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Removed decl attribute from memories

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This commit is contained in:
Jan Decaluwe 2008-09-08 17:26:53 +02:00
parent df3eb0256c
commit 0959d892ea
4 changed files with 1 additions and 7 deletions
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3
myhdl/_extractHierarchy.py
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@ -64,10 +64,9 @@ class _Instance(object):
_memInfoMap = {}
class _MemInfo(object):
__slots__ = ['mem', 'name', 'elObj', 'depth', 'decl', '_used']
__slots__ = ['mem', 'name', 'elObj', 'depth', '_used']
def __init__(self, mem):
self.mem = mem
self.decl = True
self.name = None
self.depth = len(mem)
self.elObj = mem[0]

1
myhdl/conversion/_misc.py
View File

@ -70,7 +70,6 @@ _error.NotASignal = "Non-local object should be a Signal"
_error.UnsupportedType = "Object type is not supported in this context"
_error.InconsistentType = "Signal elements should have the same base type"
_error.InconsistentBitWidth = "Signal elements should have the same bit width"
_error.ListElementNotUnique = "List contains Signals that are not unique to it"
_error.UnsupportedFormatString = "Unsupported format conversion specifier"
_error.FormatString = "Format string error"
_error.UnsupportedAttribute = "Unsupported attribute"

2
myhdl/conversion/_toVHDL.py
View File

@ -1153,8 +1153,6 @@ class _ConvertVisitor(_ConversionMixin):
elif _isMem(obj):
m = _getMemInfo(obj)
assert m.name
if not m.decl:
self.raiseError(node, _error.ListElementNotUnique, m.name)
s = m.name
elif isinstance(obj, EnumItemType):
s = obj._toVHDL()

2
myhdl/conversion/_toVerilog.py
View File

@ -837,8 +837,6 @@ class _ConvertVisitor(_ConversionMixin):
elif _isMem(obj):
m = _getMemInfo(obj)
assert m.name
if not m.decl:
self.raiseError(node, _error.ListElementNotUnique, m.name)
s = m.name
elif isinstance(obj, EnumItemType):
s = obj._toVerilog()