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support for slice signals for lists of signal members

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This commit is contained in:
Jan Decaluwe 2011-04-22 14:15:31 +02:00
parent aed50e8e3b
commit 0be158ff43
3 changed files with 23 additions and 13 deletions
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22
myhdl/_ShadowSignal.py
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@ -100,17 +100,17 @@ class _SliceSignal(_ShadowSignal):
self._sig._used = True
# def toVerilog(self):
# if self._right is None:
# return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left)
# else:
# return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right)
# def toVHDL(self):
# if self._right is None:
# return "%s <= %s(%s);" % (self._name, self._sig._name, self._left)
# else:
# return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right)
def toVerilog(self):
if self._right is None:
return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left)
else:
return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right)
def toVHDL(self):
if self._right is None:
return "%s <= %s(%s);" % (self._name, self._sig._name, self._left)
else:
return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right)

13
myhdl/conversion/_toVHDL.py
View File

@ -52,6 +52,7 @@ from myhdl.conversion._misc import (_error, _access, _kind,_context,
from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
_Ram, _Rom, _enumTypeSet)
from myhdl._Signal import _Signal,_WaiterList
from myhdl._ShadowSignal import _SliceSignal
from myhdl.conversion._toVHDLPackage import _package
_version = myhdl.__version__.replace('.','')
@ -162,7 +163,7 @@ class _ToVHDLConvertor(object):
_writeFuncDecls(vfile)
_writeSigDecls(vfile, intf, siglist, memlist)
_writeCompDecls(vfile, compDecls)
_convertGens(genlist, siglist, vfile)
_convertGens(genlist, siglist, memlist, vfile)
_writeModuleFooter(vfile)
vfile.close()
@ -355,7 +356,7 @@ def _getTypeString(s):
return 'unsigned'
def _convertGens(genlist, siglist, vfile):
def _convertGens(genlist, siglist, memlist, vfile):
blockBuf = StringIO()
funcBuf = StringIO()
for tree in genlist:
@ -396,7 +397,15 @@ def _convertGens(genlist, siglist, vfile):
for s in siglist:
if hasattr(s, 'toVHDL') and s._read:
print >> vfile, s.toVHDL()
# hack for slice signals in a list
for m in memlist:
if m._read:
for s in m.mem:
if hasattr(s, 'toVHDL'):
print >> vfile, s.toVHDL()
print >> vfile
vfile.write(blockBuf.getvalue()); blockBuf.close()

1
myhdl/conversion/_toVerilog.py
View File

@ -52,6 +52,7 @@ from myhdl.conversion._misc import (_error, _access, _kind, _context,
from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
_Ram, _Rom)
from myhdl._Signal import _Signal
from myhdl._ShadowSignal import _SliceSignal
_converting = 0
_profileFunc = None