FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

support for slice signals for lists of signal members

Browse Source
This commit is contained in:
Jan Decaluwe 2011-04-22 14:15:31 +02:00
parent aed50e8e3b
commit 0be158ff43
3 changed files with 23 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
myhdl/_ShadowSignal.py
View File

@ -100,17 +100,17 @@ class _SliceSignal(_ShadowSignal):
self._sig._used = True self._sig._used = True
# def toVerilog(self): def toVerilog(self):
# if self._right is None: if self._right is None:
# return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left) return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left)
# else: else:
# return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right) return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right)
# def toVHDL(self): def toVHDL(self):
# if self._right is None: if self._right is None:
# return "%s <= %s(%s);" % (self._name, self._sig._name, self._left) return "%s <= %s(%s);" % (self._name, self._sig._name, self._left)
# else: else:
# return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right) return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right)

13
myhdl/conversion/_toVHDL.py
View File

@ -52,6 +52,7 @@ from myhdl.conversion._misc import (_error, _access, _kind,_context,
from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc, from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
_Ram, _Rom, _enumTypeSet) _Ram, _Rom, _enumTypeSet)
from myhdl._Signal import _Signal,_WaiterList from myhdl._Signal import _Signal,_WaiterList
from myhdl._ShadowSignal import _SliceSignal
from myhdl.conversion._toVHDLPackage import _package from myhdl.conversion._toVHDLPackage import _package
_version = myhdl.__version__.replace('.','') _version = myhdl.__version__.replace('.','')
@ -162,7 +163,7 @@ class _ToVHDLConvertor(object):
_writeFuncDecls(vfile) _writeFuncDecls(vfile)
_writeSigDecls(vfile, intf, siglist, memlist) _writeSigDecls(vfile, intf, siglist, memlist)
_writeCompDecls(vfile, compDecls) _writeCompDecls(vfile, compDecls)
_convertGens(genlist, siglist, vfile) _convertGens(genlist, siglist, memlist, vfile)
_writeModuleFooter(vfile) _writeModuleFooter(vfile)
vfile.close() vfile.close()
@ -355,7 +356,7 @@ def _getTypeString(s):
return 'unsigned' return 'unsigned'
def _convertGens(genlist, siglist, vfile): def _convertGens(genlist, siglist, memlist, vfile):
blockBuf = StringIO() blockBuf = StringIO()
funcBuf = StringIO() funcBuf = StringIO()
for tree in genlist: for tree in genlist:
@ -396,7 +397,15 @@ def _convertGens(genlist, siglist, vfile):
for s in siglist: for s in siglist:
if hasattr(s, 'toVHDL') and s._read: if hasattr(s, 'toVHDL') and s._read:
print >> vfile, s.toVHDL() print >> vfile, s.toVHDL()
# hack for slice signals in a list
for m in memlist:
if m._read:
for s in m.mem:
if hasattr(s, 'toVHDL'):
print >> vfile, s.toVHDL()
print >> vfile print >> vfile
vfile.write(blockBuf.getvalue()); blockBuf.close() vfile.write(blockBuf.getvalue()); blockBuf.close()

1
myhdl/conversion/_toVerilog.py
View File

@ -52,6 +52,7 @@ from myhdl.conversion._misc import (_error, _access, _kind, _context,
from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc, from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
_Ram, _Rom) _Ram, _Rom)
from myhdl._Signal import _Signal from myhdl._Signal import _Signal
from myhdl._ShadowSignal import _SliceSignal
_converting = 0 _converting = 0
_profileFunc = None _profileFunc = None