mirror of
https://github.com/myhdl/myhdl.git
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Binops convert in VHDL fix (#404)
* Add tests that shows failing case, in VHDL. When many unsigned, single bit signals are BinOped together (Or'ed in this case) to a boolean (std_logic). Verilog works * Remove clk from design where it is not used * Update tests to find more corner cases * Add dest to rhs signal to allow the destination signal to be rippled along the chain if there are multiple elements/signals being assigned
This commit is contained in:
Dave Keeshan
GitHub
parent
7c6a5fda54
commit
0c38f9441b
@ -881,14 +881,25 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.write(suf)
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def BitOp(self, node):
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pre, suf = self.inferCast(node.vhd, node.vhdOri)
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self.write(pre)
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lpre = lsuf = ""
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rpre = rsuf = ""
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if hasattr(node, 'dest'):
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node.left.dest = node.dest
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node.right.dest = node.dest
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if isinstance(node.left, ast.Name):
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lpre, lsuf = self.inferCast(node.dest.vhd, node.left.vhd)
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if isinstance(node.right, ast.Name):
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rpre, rsuf = self.inferCast(node.dest.vhd, node.right.vhd)
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self.write("(")
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self.write(lpre)
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self.visit(node.left)
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self.write(lsuf)
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self.write(" %s " % opmap[type(node.op)])
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self.write(rpre)
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self.visit(node.right)
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self.write(rsuf)
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self.write(")")
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self.write(suf)
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def visit_BoolOp(self, node):
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if isinstance(node.vhd, vhd_std_logic):
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@ -1031,6 +1042,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.visit(lhs)
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self.isLhs = False
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if self.SigAss:
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rhs.dest = lhs.value
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if isinstance(lhs.value, ast.Name):
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sig = self.tree.symdict[lhs.value.id]
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self.write(' <= ')
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450
myhdl/test/conversion/general/test_binops.py
Normal file
450
myhdl/test/conversion/general/test_binops.py
Normal file
@ -0,0 +1,450 @@
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from myhdl import *
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@block
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def binOpsCheck0(
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a,
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b,
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c,
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x,
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y,
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z,
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):
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@always_comb
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def outputs():
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x.next = a
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y.next = a | b
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z.next = a | b | c
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return instances()
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@block
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def binOpsCheck1(
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a,
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x,
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y,
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z,
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):
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@always_comb
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def outputs():
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x.next = a[0]
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y.next = a[0] | a[1]
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z.next = a[0] | a[1] | a[2]
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return instances()
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@block
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def binOpsCheck2(
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a,
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z,
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):
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@always_comb
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def outputs():
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z[0].next = a[0]
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z[1].next = a[0] | a[1]
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z[2].next = a[0] | a[1] | a[2]
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return instances()
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@block
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def binOpsCheckBench0():
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clk = Signal(bool(0))
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a = Signal(modbv(0)[1:])
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b = Signal(modbv(0)[1:])
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c = Signal(modbv(0)[1:])
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x = Signal(modbv(0)[1:])
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y = Signal(modbv(0)[1:])
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z = Signal(modbv(0)[1:])
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@instance
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def clkgen():
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clk.next = 1
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for i in range(400):
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yield delay(10)
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clk.next = not clk
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@instance
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def stimulus():
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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a.next = 0x0
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x1
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yield clk.posedge
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a.next = 0x1
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b.next = 0x0
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c.next = 0x1
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yield clk.posedge
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a.next = 0x0
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x1
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c.next = 0x1
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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raise StopSimulation
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@instance
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def check():
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x0
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x0
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yield clk.posedge
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i_binOpsCheck = binOpsCheck0(a, b, c, x, y, z)
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return instances()
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@block
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def binOpsCheckBench1():
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clk = Signal(bool(0))
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a = Signal(modbv(0)[1:])
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b = Signal(modbv(0)[1:])
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c = Signal(modbv(0)[1:])
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x = Signal(False)
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y = Signal(False)
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z = Signal(False)
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@instance
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def clkgen():
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clk.next = 1
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for i in range(400):
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yield delay(10)
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clk.next = not clk
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@instance
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def stimulus():
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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a.next = 0x0
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x1
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yield clk.posedge
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a.next = 0x1
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b.next = 0x0
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c.next = 0x1
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yield clk.posedge
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a.next = 0x0
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x1
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c.next = 0x1
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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raise StopSimulation
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@instance
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def check():
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x0
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x0
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yield clk.posedge
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i_binOpsCheck = binOpsCheck0(a, b, c, x, y, z)
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return instances()
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@block
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def binOpsCheckBench2():
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clk = Signal(bool(0))
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a = Signal(modbv(0)[2:])
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b = Signal(modbv(0)[2:])
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c = Signal(modbv(0)[2:])
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x = Signal(modbv(0)[2:])
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y = Signal(modbv(0)[2:])
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z = Signal(modbv(0)[2:])
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@instance
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def clkgen():
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clk.next = 1
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for i in range(400):
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yield delay(10)
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clk.next = not clk
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@instance
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def stimulus():
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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a.next = 0x0
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x1
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yield clk.posedge
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a.next = 0x1
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b.next = 0x0
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c.next = 0x1
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yield clk.posedge
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a.next = 0x0
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b.next = 0x1
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c.next = 0x0
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yield clk.posedge
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a.next = 0x1
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b.next = 0x1
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c.next = 0x1
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yield clk.posedge
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a.next = 0x0
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b.next = 0x0
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c.next = 0x0
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yield clk.posedge
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raise StopSimulation
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@instance
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def check():
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x0
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x1
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assert y == 0x1
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assert z == 0x1
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yield clk.posedge
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assert x == 0x0
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assert y == 0x0
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assert z == 0x0
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yield clk.posedge
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i_binOpsCheck = binOpsCheck0(a, b, c, x, y, z)
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return instances()
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def test_binOps0():
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sim = binOpsCheckBench0()
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sim.run_sim()
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def test_binOps0_convert():
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i_dut = binOpsCheckBench0()
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assert i_dut.analyze_convert() == 0
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#assert i_dut.verify_simulator() == 0
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#assert i_dut.verify_convert() == 0
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def test_binOps1():
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sim = binOpsCheckBench1()
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sim.run_sim()
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def test_binOps1_convert():
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i_dut = binOpsCheckBench1()
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assert i_dut.analyze_convert() == 0
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#assert i_dut.verify_simulator() == 0
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def test_binOps1b_convert():
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a = Signal(modbv(0)[1:])
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b = Signal(modbv(0)[1:])
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c = Signal(modbv(0)[1:])
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x = Signal(False)
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y = Signal(False)
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z = Signal(False)
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i_dut = binOpsCheck0(a, b, c, x, y, z)
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assert i_dut.analyze_convert() == 0
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def test_binOps1c_convert():
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a = Signal(intbv(0)[1:])
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b = Signal(intbv(0)[1:])
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c = Signal(intbv(0)[1:])
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x = Signal(False)
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y = Signal(False)
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z = Signal(False)
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i_dut = binOpsCheck0(a, b, c, x, y, z)
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assert i_dut.analyze_convert() == 0
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def test_binOps1d_convert():
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a = Signal(intbv(0)[3:])
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x = Signal(False)
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y = Signal(False)
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z = Signal(False)
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i_dut = binOpsCheck1(a, x, y, z)
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assert i_dut.analyze_convert() == 0
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def test_binOps1e_convert():
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a = Signal(intbv(0)[3:])
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z = Signal(intbv(0)[3:])
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i_dut = binOpsCheck2(a, z)
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assert i_dut.analyze_convert() == 0
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def test_binOps2():
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sim = binOpsCheckBench2()
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sim.run_sim()
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def test_binOps2_convert():
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i_dut = binOpsCheckBench2()
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assert i_dut.analyze_convert() == 0
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#assert i_dut.verify_convert() == 0
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#assert i_dut.verify_simulator() == 0
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