FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

added

Browse Source
This commit is contained in:
jand 2004-02-03 14:30:03 +00:00
parent 4405eac0c9
commit 0c7cca721b
2 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
myhdl/test/toVerilog/README.txt Normal file
View File

@ -0,0 +1,3 @@
The tests in this directory require a working Icarus installation
(iverilog and vvp commands), because co-simulation with Icarus Verilog
is used to verify the Verilog designs generated by the converter.

7
myhdl/test/toVerilog/test_all.py
View File

@ -23,6 +23,9 @@ __author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
__revision__ = "$Revision$"
__date__ = "$Date$"
import os
import unittest
import test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \
test_inc_initial, test_hec, test_loops, test_infer, test_errors, \
test_RandomScrambler, test_beh, test_GrayInc
@ -33,7 +36,6 @@ modules = (test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \
test_RandomScrambler, test_beh, test_GrayInc
)
import unittest
tl = unittest.defaultTestLoader
def suite():
@ -45,7 +47,8 @@ def suite():
def main():
unittest.main(defaultTest='suite',
testRunner=unittest.TextTestRunner(verbosity=2))
if __name__ == '__main__':
main()