From 0c7cca721b2df4cec379ea8db28bb350c4191747 Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Tue, 3 Feb 2004 14:30:03 +0000
Subject: [PATCH] added

---
 myhdl/test/toVerilog/README.txt  | 3 +++
 myhdl/test/toVerilog/test_all.py | 7 +++++--
 2 files changed, 8 insertions(+), 2 deletions(-)
 create mode 100644 myhdl/test/toVerilog/README.txt

diff --git a/myhdl/test/toVerilog/README.txt b/myhdl/test/toVerilog/README.txt
new file mode 100644
index 00000000..e45873b9
--- /dev/null
+++ b/myhdl/test/toVerilog/README.txt
@@ -0,0 +1,3 @@
+The tests in this directory require a working Icarus installation
+(iverilog and vvp commands), because co-simulation with Icarus Verilog
+is used to verify the Verilog designs generated by the converter.
diff --git a/myhdl/test/toVerilog/test_all.py b/myhdl/test/toVerilog/test_all.py
index 43361687..e0154884 100644
--- a/myhdl/test/toVerilog/test_all.py
+++ b/myhdl/test/toVerilog/test_all.py
@@ -23,6 +23,9 @@ __author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
 __revision__ = "$Revision$"
 __date__ = "$Date$"
 
+import os
+import unittest
+
 import test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \
        test_inc_initial, test_hec, test_loops, test_infer, test_errors, \
        test_RandomScrambler, test_beh, test_GrayInc
@@ -33,7 +36,6 @@ modules = (test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \
            test_RandomScrambler, test_beh, test_GrayInc
            )
 
-import unittest
 
 tl = unittest.defaultTestLoader
 def suite():
@@ -45,7 +47,8 @@ def suite():
 def main():
     unittest.main(defaultTest='suite',
                   testRunner=unittest.TextTestRunner(verbosity=2))
-    
+
+
 
 if __name__ == '__main__':
     main()