From 0d6a5d78d0fdb273ab0c355463f0a17eeb74f3c0 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 2 Sep 2016 15:45:03 -0400 Subject: [PATCH] made import statement in _toVHDL.py more specific and fixed warning in _VHDLNameValidation --- myhdl/conversion/_VHDLNameValidation.py | 11 ++++++----- myhdl/conversion/_toVHDL.py | 8 ++++---- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index e8e27f77..28ab471a 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -1,5 +1,6 @@ import warnings from myhdl import * +from myhdl import ToVHDLWarning from myhdl.conversion import _analyze import pytest @@ -34,13 +35,13 @@ _usedNames = []; def _nameValid(name): for keyword in _vhdl_keywords: if name == keyword: - warnings.warn("VHDL keyword used: %s" % name, category=ToVHDLWarning) + warnings.warn("VHDL keyword used: %s" % (name), category=ToVHDLWarning) for saved_name in _usedNames: if name.lower() == saved_name: - warnings.warn("Previously used name being reused: %s" % name, category=ToVHDLWarning) - _usedNames.append(name).lower + warnings.warn("Previously used name being reused: %s" % (name), category=ToVHDLWarning) + _usedNames.append(name.lower()) if name[0] == '_': - warnings.warn("VHDL variable names cannot contain '_': %s" % name, category=ToVHDLWarning) + warnings.warn("VHDL variable names cannot contain '_': %s" % (name), category=ToVHDLWarning) for char in name: if char == '-': - warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning) + warnings.warn("VHDL variable names cannot contain '-': %s" % (name), category=ToVHDLWarning) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 980ad4bb..4b734ec2 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -55,7 +55,7 @@ from myhdl.conversion._toVHDLPackage import _package from myhdl._util import _flatten from myhdl._compat import integer_types, class_types, StringIO from myhdl._ShadowSignal import _TristateSignal, _TristateDriver -import myhdl.conversion._VHDLNameValidation +from myhdl.conversion._VHDLNameValidation import _nameValid from myhdl._block import _Block @@ -354,7 +354,7 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor if convertPort: pt = "std_logic_vector" # Check if VHDL keyword or reused name - _VHDLNameValidation._nameValid(s) + _nameValid(s) if s._driven: if s._read: if not isinstance(s, _TristateSignal): @@ -419,7 +419,7 @@ def _writeSigDecls(f, intf, siglist, memlist): print("signal %s: %s%s;" % (s._name, p, r), file=f) elif s._read: # Check if VHDL keyword or reused name - _VHDLNameValidation._nameValid(s) + _nameValid(s) # the original exception # raise ToVHDLError(_error.UndrivenSignal, s._name) # changed to a warning and a continuous assignment to a wire @@ -440,7 +440,7 @@ def _writeSigDecls(f, intf, siglist, memlist): if not m._driven and not m._read: continue # Check if VHDL keyword or reused name - _VHDLNameValidation._nameValid(m) + _nameValid(m) r = _getRangeString(m.elObj) p = _getTypeString(m.elObj) t = "t_array_%s" % m.name