updated preface

doc/source/manual/preface.rst

@@ -1,39 +1,36 @@
-*******
+********
-Preface
+Overview
-*******
+********
 
+The goal of the MyHDL project is to empower hardware designers with
+the elegance and simplicity of the Python language.
 
-The goal of the MyHDL project is to empower hardware designers with the elegance
+MyHDL is a free, open-source (LGPL) package for using Python as a
-and simplicity of the Python language.
+hardware description and verification language. Python is a very high
-
+level language, and hardware designers can use its full power to model
-MyHDL is a free, open-source (LGPL) package for using Python as a hardware
+and simulate their designs.  Moreover, MyHDL can convert a design to
-description and verification language. Python is a very high level language, and
+Verilog or VHDL. This provides a path into a traditional design flow.
-hardware designers can use its full power to model and simulate their designs.
-Moreover, MyHDL can convert a design to Verilog or VHDL. In combination with an external
-synthesis tool, this provides a complete path from Python to a silicon
-implementation.
 
 *Modeling*
 
-Python's power and clarity make MyHDL an ideal solution for high level modeling.
+Python's power and clarity make MyHDL an ideal solution for high level
-Python is famous for enabling elegant solutions to complex modeling problems.
+modeling.  Python is famous for enabling elegant solutions to complex
-Moreover, Python is outstanding for rapid application development and
+modeling problems.  Moreover, Python is outstanding for rapid
-experimentation.
+application development and experimentation.
 
-The key idea behind MyHDL is the use of Python generators to model hardware
+The key idea behind MyHDL is the use of Python generators to model
-concurrency. Generators are best described as resumable functions. In MyHDL,
+hardware concurrency. Generators are best described as resumable
-generators are used in a specific way so that they become similar to always
+functions.  MyHDL generators are similar to always blocks in Verilog
-blocks in Verilog or processes in VHDL.
+and processes in VHDL.
 
-A hardware module is modeled as a function that returns any number of
+A hardware module is modeled as a function that returns
-generators. This approach makes it straightforward to support features such as
+generators. This approach makes it straightforward to support features
-arbitrary hierarchy, named port association, arrays of instances, and
+such as arbitrary hierarchy, named port association, arrays of
-conditional instantiation.
+instances, and conditional instantiation.  Furthermore, MyHDL provides
-
+classes that implement traditional hardware description concepts. It
-Furthermore, MyHDL provides classes that implement traditional hardware
+provides a signal class to support communication between generators, a
-description concepts. It provides a signal class to support communication
+class to support bit oriented operations, and a class for enumeration
-between generators, a class to support bit oriented operations, and a class for
+types.
-enumeration types.
 
 *Simulation and Verification*
 
@@ -42,17 +39,25 @@ waveform viewing by tracing signal changes in a VCD file.
 
 With MyHDL, the Python unit test framework can be used on hardware designs.
 Although unit testing is a popular modern software verification technique, it is
-not yet common in the hardware design world, making it one more area in which
+still uncommon in the hardware design world.
-MyHDL innovates.
 
 MyHDL can also be used as hardware verification language for Verilog
 designs, by co-simulation with traditional HDL simulators.
 
 *Conversion to Verilog and VHDL*
 
-MyHDL designs can be converted to Verilog or VHDL, if certain coding
+Subject to some limitations, MyHDL designs can be converted to Verilog
-restrictions are obeyed.
+or VHDL.  This provides a path into a traditional design flow,
-The conversion works on an instantiated design that has been fully
+including synthesis and implementation.  However, the convertible
-elaborated. Consequently, the original design structure can be arbitrarily
+subset is much wider than the standard synthesis subset, and includes
-complex.
+features that can be used for high level modeling and test benches.
 
+The converter to Verilog works on an instantiated design that has been
+fully elaborated. Consequently, the original design structure can be
+arbitrarily complex. Moreover, the conversion limitations only apply
+to code inside generators. Outside generators, Python's full power can
+be used without compromising convertibility.
+
+Finally, the converter automates a number of tasks that are hard in
+Verilog directly. A notable feature is the automated handling of
+signed arithmetic issues.