FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

Merged in svenstaro/myhdl//fix-docs-this-is-actually-just-3-variabl-1397165148577 (pull request #9)

Browse Source 
Fix docs, this is actually just 3 variables
This commit is contained in:
jandecaluwe 2014-04-11 17:14:48 +02:00
commit 0e268cbf23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/source/manual/rtl.rst
View File

@ -191,7 +191,7 @@ the :func:`StopSimulation()` exception to stop the simulation run. The test benc
a small incrementer and a small number of patterns is a follows:: a small incrementer and a small number of patterns is a follows::
def testbench(): def testbench():
count, enable, clock = [Signal(intbv(0)) for i in range(4)] count, enable, clock = [Signal(intbv(0)) for i in range(3)]
reset = ResetSignal(0, active=ACTIVE_LOW, async=True) reset = ResetSignal(0, active=ACTIVE_LOW, async=True)
inc_1 = Inc(count, enable, clock, reset, n=4) inc_1 = Inc(count, enable, clock, reset, n=4)