diff --git a/myhdl/test/bugs/test_issue_185.py b/myhdl/test/bugs/test_issue_185.py
new file mode 100644
index 00000000..2b125df1
--- /dev/null
+++ b/myhdl/test/bugs/test_issue_185.py
@@ -0,0 +1,30 @@
+from myhdl import *
+
+def shift_left(c, a, b):
+    c.next = a << b
+
+@block
+def shifter(reset, clock, opa, opb, result):
+    
+    @always_seq(clock.posedge, reset = reset)
+    def assign():
+        shift_left(result, opa, opb)
+
+    return assign
+
+
+def convert():
+
+    clock = Signal(bool(0))
+    reset = ResetSignal(0, active=True, async=True)
+
+    opa = Signal(intbv(0)[4:])
+    opb = Signal(intbv(0)[4:])
+    result = Signal(intbv(0)[10:])
+
+    inst = shifter(reset, clock, opa, opb, result)
+    inst.convert(hdl='VHDL')
+
+
+if __name__ == '__main__':
+    convert()