Updated tests to new block style and also changed no_initial_values -> initial_values

myhdl/conversion/_toVHDL.py

@@ -113,7 +113,7 @@ class _ToVHDLConvertor(object):
                  "use_clauses",
                  "architecture",
                  "std_logic_ports",
-                 "no_initial_values"
+                 "initial_values"
                  )
 
     def __init__(self):
@@ -127,7 +127,7 @@ class _ToVHDLConvertor(object):
         self.use_clauses = None
         self.architecture = "MyHDL"
         self.std_logic_ports = False
-        self.no_initial_values = True
+        self.initial_values = False
 
     def __call__(self, func, *args, **kwargs):
         global _converting
@@ -416,7 +416,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
 
             sig_vhdl_obj = inferVhdlObj(s)
 
-            if toVHDL.no_initial_values:
+            if not toVHDL.initial_values:
                 val_str = ""
             else:
 

myhdl/conversion/_toVerilog.py

@@ -108,7 +108,7 @@ class _ToVerilogConvertor(object):
                  "no_testbench",
                  "portmap",
                  "trace",
-                 "no_initial_values"
+                 "initial_values"
                  )
 
     def __init__(self):
@@ -122,7 +122,7 @@ class _ToVerilogConvertor(object):
         self.no_myhdl_header = False
         self.no_testbench = False
         self.trace = False
-        self.no_initial_values = True
+        self.initial_values = False
 
     def __call__(self, func, *args, **kwargs):
         global _converting
@@ -331,7 +331,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
             # the following line implements initial value assignments
             # don't initial value "wire", inital assignment to a wire
             # equates to a continuous assignment [reference]
-            if toVerilog.no_initial_values or k == 'wire':
+            if not toVerilog.initial_values or k == 'wire':
                 print("%s %s%s%s;" % (k, p, r, s._name), file=f)
             else:
                 print("%s %s%s%s = %s;" % 

myhdl/test/conversion/general/test_initial_values.py

@@ -4,6 +4,7 @@ from random import randrange
 from myhdl import *
 import myhdl
 
+@block
 def initial_value_bench(initial_val, change_input_signal):
 
     clk = Signal(bool(0))
@@ -63,17 +64,17 @@ def initial_value_bench(initial_val, change_input_signal):
     return clkgen, output_driver, drive_and_check, output_writer
 
 def runner(initial_val, change_input_signal=False):
-    pre_toVerilog_no_initial_values = toVerilog.no_initial_values
-    pre_toVHDL_no_initial_values = toVerilog.no_initial_values
+    pre_toVerilog_initial_values = toVerilog.initial_values
+    pre_toVHDL_initial_values = toVerilog.initial_values
 
-    toVerilog.no_initial_values = False
-    toVHDL.no_initial_values = False
+    toVerilog.initial_values = True
+    toVHDL.initial_values = True
 
     assert conversion.verify(
-        initial_value_bench, initial_val, change_input_signal) == 0
+        initial_value_bench(initial_val, change_input_signal)) == 0
     
-    toVerilog.no_initial_values = pre_toVerilog_no_initial_values
-    toVHDL.no_initial_values = pre_toVHDL_no_initial_values
+    toVerilog.initial_values = pre_toVerilog_initial_values
+    toVHDL.initial_values = pre_toVHDL_initial_values
 
 def test_unsigned():
     '''The correct initial value should be used for unsigned type signal.