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Updated tests to new block style and also changed no_initial_values -> initial_values

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This commit is contained in:
Henry Gomersall 2016-05-04 13:32:29 +01:00
parent cc39cda77e
commit 0edc13bf5f
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GPG Key ID: 67F4313D73CED5A6
3 changed files with 14 additions and 13 deletions
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6
myhdl/conversion/_toVHDL.py
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@ -113,7 +113,7 @@ class _ToVHDLConvertor(object):
"use_clauses", "use_clauses",
"architecture", "architecture",
"std_logic_ports", "std_logic_ports",
"no_initial_values" "initial_values"
) )
def __init__(self): def __init__(self):
@ -127,7 +127,7 @@ class _ToVHDLConvertor(object):
self.use_clauses = None self.use_clauses = None
self.architecture = "MyHDL" self.architecture = "MyHDL"
self.std_logic_ports = False self.std_logic_ports = False
self.no_initial_values = True self.initial_values = False
def __call__(self, func, *args, **kwargs): def __call__(self, func, *args, **kwargs):
global _converting global _converting
@ -416,7 +416,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
sig_vhdl_obj = inferVhdlObj(s) sig_vhdl_obj = inferVhdlObj(s)
if toVHDL.no_initial_values: if not toVHDL.initial_values:
val_str = "" val_str = ""
else: else:

6
myhdl/conversion/_toVerilog.py
View File

@ -108,7 +108,7 @@ class _ToVerilogConvertor(object):
"no_testbench", "no_testbench",
"portmap", "portmap",
"trace", "trace",
"no_initial_values" "initial_values"
) )
def __init__(self): def __init__(self):
@ -122,7 +122,7 @@ class _ToVerilogConvertor(object):
self.no_myhdl_header = False self.no_myhdl_header = False
self.no_testbench = False self.no_testbench = False
self.trace = False self.trace = False
self.no_initial_values = True self.initial_values = False
def __call__(self, func, *args, **kwargs): def __call__(self, func, *args, **kwargs):
global _converting global _converting
@ -331,7 +331,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
# the following line implements initial value assignments # the following line implements initial value assignments
# don't initial value "wire", inital assignment to a wire # don't initial value "wire", inital assignment to a wire
# equates to a continuous assignment [reference] # equates to a continuous assignment [reference]
if toVerilog.no_initial_values or k == 'wire': if not toVerilog.initial_values or k == 'wire':
print("%s %s%s%s;" % (k, p, r, s._name), file=f) print("%s %s%s%s;" % (k, p, r, s._name), file=f)
else: else:
print("%s %s%s%s = %s;" % print("%s %s%s%s = %s;" %

15
myhdl/test/conversion/general/test_initial_values.py
View File

@ -4,6 +4,7 @@ from random import randrange
from myhdl import * from myhdl import *
import myhdl import myhdl
@block
def initial_value_bench(initial_val, change_input_signal): def initial_value_bench(initial_val, change_input_signal):
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -63,17 +64,17 @@ def initial_value_bench(initial_val, change_input_signal):
return clkgen, output_driver, drive_and_check, output_writer return clkgen, output_driver, drive_and_check, output_writer
def runner(initial_val, change_input_signal=False): def runner(initial_val, change_input_signal=False):
pre_toVerilog_no_initial_values = toVerilog.no_initial_values pre_toVerilog_initial_values = toVerilog.initial_values
pre_toVHDL_no_initial_values = toVerilog.no_initial_values pre_toVHDL_initial_values = toVerilog.initial_values
toVerilog.no_initial_values = False toVerilog.initial_values = True
toVHDL.no_initial_values = False toVHDL.initial_values = True
assert conversion.verify( assert conversion.verify(
initial_value_bench, initial_val, change_input_signal) == 0 initial_value_bench(initial_val, change_input_signal)) == 0
toVerilog.no_initial_values = pre_toVerilog_no_initial_values toVerilog.initial_values = pre_toVerilog_initial_values
toVHDL.no_initial_values = pre_toVHDL_no_initial_values toVHDL.initial_values = pre_toVHDL_initial_values
def test_unsigned(): def test_unsigned():
'''The correct initial value should be used for unsigned type signal. '''The correct initial value should be used for unsigned type signal.