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mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00

started going through package always for import

This commit is contained in:
jand 2003-07-20 07:59:08 +00:00
parent 509a57a82c
commit 1119554f26
3 changed files with 21 additions and 7 deletions

View File

@ -33,8 +33,8 @@ __date__ = "$Date$"
from __future__ import generators
from copy import deepcopy as copy
import _simulator as sim
from _simulator import _siglist, _futureEvents, now
from myhdl import _simulator as sim
from myhdl._simulator import _siglist, _futureEvents, now
from myhdl import intbv
from bin import bin

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@ -34,9 +34,9 @@ import types
import unittest
from unittest import TestCase
from Signal import Signal
from _simulator import _siglist
from myhdl._simulator import _siglist
from myhdl import intbv
from Signal import Signal
class SigTest(TestCase):

View File

@ -35,13 +35,23 @@ import string
import time
from util import _isGenSeq
from myhdl import _simulator
from myhdl import Signal, __version__
import _simulator
_tracing = 0
class Error(Exception):
pass
""" trace_sigs Error"""
def __init__(self, arg=""):
self.arg = arg
def __str__(self):
msg = self.__doc__
if self.arg:
msg = msg + ": " + str(self.arg)
return msg
class TopLevelNameError(Error):
""" result of trace_sigs call should be assigned to a top level name """
re_assname = re.compile(r"^\s*(?P<assname>\w[\w\d]*)\s*=")
@ -57,12 +67,15 @@ def trace_sigs(dut, *args, **kwargs):
if m:
name = m.group('assname')
else:
raise Error
raise TopLevelNameError
h = HierExtr(name, dut, *args, **kwargs)
vcdfilename = name + ".vcd"
vcdfile = open(vcdfilename, 'w')
_simulator._tracing = 1
_simulator._tf = vcdfile
print "TRACE"
print _simulator
print _simulator._tf
_writeVcdHeader(vcdfile)
_writeVcdSigs(vcdfile, h.instances)
_tracing = 0
@ -171,6 +184,7 @@ def _writeVcdSigs(f, instances):
print >> f
print >> f, "$enddefinitions $end"
print >> f, "$dumpvars"
print f
for s in siglist:
s._printVcd() # initial value
print >> f, "$end"