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started going through package always for import
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@ -33,8 +33,8 @@ __date__ = "$Date$"
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from __future__ import generators
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from copy import deepcopy as copy
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import _simulator as sim
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from _simulator import _siglist, _futureEvents, now
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from myhdl import _simulator as sim
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from myhdl._simulator import _siglist, _futureEvents, now
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from myhdl import intbv
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from bin import bin
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@ -34,9 +34,9 @@ import types
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import unittest
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from unittest import TestCase
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from Signal import Signal
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from _simulator import _siglist
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from myhdl._simulator import _siglist
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from myhdl import intbv
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from Signal import Signal
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class SigTest(TestCase):
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@ -35,13 +35,23 @@ import string
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import time
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from util import _isGenSeq
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from myhdl import _simulator
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from myhdl import Signal, __version__
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import _simulator
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_tracing = 0
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class Error(Exception):
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pass
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""" trace_sigs Error"""
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def __init__(self, arg=""):
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self.arg = arg
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def __str__(self):
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msg = self.__doc__
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if self.arg:
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msg = msg + ": " + str(self.arg)
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return msg
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class TopLevelNameError(Error):
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""" result of trace_sigs call should be assigned to a top level name """
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re_assname = re.compile(r"^\s*(?P<assname>\w[\w\d]*)\s*=")
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@ -57,12 +67,15 @@ def trace_sigs(dut, *args, **kwargs):
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if m:
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name = m.group('assname')
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else:
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raise Error
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raise TopLevelNameError
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h = HierExtr(name, dut, *args, **kwargs)
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vcdfilename = name + ".vcd"
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vcdfile = open(vcdfilename, 'w')
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_simulator._tracing = 1
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_simulator._tf = vcdfile
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print "TRACE"
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print _simulator
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print _simulator._tf
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_writeVcdHeader(vcdfile)
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_writeVcdSigs(vcdfile, h.instances)
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_tracing = 0
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@ -171,6 +184,7 @@ def _writeVcdSigs(f, instances):
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print >> f
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print >> f, "$enddefinitions $end"
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print >> f, "$dumpvars"
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print f
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for s in siglist:
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s._printVcd() # initial value
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print >> f, "$end"
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