From 1137934141f60da8047c5172e324ecf387eabe29 Mon Sep 17 00:00:00 2001 From: Jan Decaluwe Date: Sun, 14 Feb 2016 17:32:59 +0100 Subject: [PATCH] Adapt traceSignals; migrate test --- myhdl/_traceSignals.py | 40 ++++++++++++++----- myhdl/test/core/test_traceSignals.py | 59 +++++++++++++++------------- 2 files changed, 62 insertions(+), 37 deletions(-) diff --git a/myhdl/_traceSignals.py b/myhdl/_traceSignals.py index abd8dd5a..b1c817df 100644 --- a/myhdl/_traceSignals.py +++ b/myhdl/_traceSignals.py @@ -35,9 +35,12 @@ from myhdl import _simulator, __version__, EnumItemType from myhdl._extractHierarchy import _HierExtr from myhdl import TraceSignalsError from myhdl._ShadowSignal import _TristateSignal, _TristateDriver +from myhdl._module import _Module, _ModuleInstance +from myhdl._getHierarchy import _getHierarchy _tracing = 0 _profileFunc = None +vcdpath = '' class _error: pass @@ -61,17 +64,27 @@ class _TraceSignalsClass(object): self.tracelists = True def __call__(self, dut, *args, **kwargs): - global _tracing - if _tracing: - return dut(*args, **kwargs) # skip - else: - # clean start - sys.setprofile(None) + global _tracing, vcdpath + if isinstance(dut, _ModuleInstance): + # now we go bottom-up: so clean up and start over + # TODO: consider a warning for the overruled module + if _simulator._tracing: + _simulator._tracing = 0 + _simulator._tf.close() + os.remove(vcdpath) + else: # deprecated + if _tracing: + return dut(*args, **kwargs) # skip + else: + # clean start + sys.setprofile(None) + from myhdl.conversion import _toVerilog if _toVerilog._converting: raise TraceSignalsError("Cannot use traceSignals while converting to Verilog") - if not callable(dut): - raise TraceSignalsError(_error.ArgType, "got %s" % type(dut)) + if not isinstance(dut, _ModuleInstance): + if not callable(dut): + raise TraceSignalsError(_error.ArgType, "got %s" % type(dut)) if _simulator._tracing: raise TraceSignalsError(_error.MultipleTraces) @@ -79,6 +92,8 @@ class _TraceSignalsClass(object): try: if self.name is None: name = dut.__name__ + if isinstance(dut, _ModuleInstance): + name = dut.mod.__name__ else: name = str(self.name) if name is None: @@ -89,7 +104,14 @@ class _TraceSignalsClass(object): else: directory = self.directory - h = _HierExtr(name, dut, *args, **kwargs) + if isinstance(dut, _Module): + raise TypeError("Module %s: conversion should be on an instance" % dut.__name__) + + if isinstance(dut, _ModuleInstance): + h = _getHierarchy(name, dut) + else: + h = _HierExtr(name, dut, *args, **kwargs) + vcdpath = os.path.join(directory, name + ".vcd") if path.exists(vcdpath): backup = vcdpath + '.' + str(path.getmtime(vcdpath)) diff --git a/myhdl/test/core/test_traceSignals.py b/myhdl/test/core/test_traceSignals.py index 00f3a65d..8347ca51 100644 --- a/myhdl/test/core/test_traceSignals.py +++ b/myhdl/test/core/test_traceSignals.py @@ -25,7 +25,7 @@ import random import pytest -from myhdl import Signal, Simulation, _simulator, delay, instance, intbv +from myhdl import Signal, Simulation, _simulator, delay, instance, intbv, module from myhdl._traceSignals import TraceSignalsError, _error, traceSignals from helpers import raises_kind @@ -35,7 +35,7 @@ path = os.path QUIET=1 - +@module def gen(clk): @instance def logic(): @@ -44,37 +44,37 @@ def gen(clk): clk.next = not clk return logic - +@module def fun(): clk = Signal(bool(0)) inst = gen(clk) return inst - +@module def dummy(): clk = Signal(bool(0)) inst = gen(clk) return 1 - +@module def top(): - inst = traceSignals(fun) + inst = traceSignals(fun()) return inst - +@module def top2(): inst = [{} for i in range(4)] j = 3 - inst[j-2]['key'] = traceSignals(fun) + inst[j-2]['key'] = traceSignals(fun()) return inst - +@module def top3(): - inst_1 = traceSignals(fun) - inst_2 = traceSignals(fun) + inst_1 = traceSignals(fun()) + inst_2 = traceSignals(fun()) return inst_1, inst_2 - +@module def genTristate(clk, x, y, z): xd = x.driver() yd = y.driver() @@ -99,7 +99,7 @@ def genTristate(clk, x, y, z): yd.next = zd.next = 0 return ckgen,logic - +@module def tristate(): from myhdl import TristateSignal clk = Signal(bool(0)) @@ -110,9 +110,9 @@ def tristate(): inst = genTristate(clk, x, y, z) return inst - +@module def topTristate(): - inst = traceSignals(tristate) + inst = traceSignals(tristate()) return inst @@ -127,20 +127,23 @@ def vcd_dir(tmpdir): class TestTraceSigs: - def testMultipleTraces(self, vcd_dir): - with raises_kind(TraceSignalsError, _error.MultipleTraces): - dut = top3() + # TODO: multiple trace handling is different now has the + # calls go bottom-up. To be revisited. + # def testMultipleTraces(self, vcd_dir): + # with raises_kind(TraceSignalsError, _error.MultipleTraces): + # dut = top3() def testArgType1(self, vcd_dir): with raises_kind(TraceSignalsError, _error.ArgType): dut = traceSignals([1, 2]) - def testReturnVal(self, vcd_dir): - from myhdl import ExtractHierarchyError - from myhdl._extractHierarchy import _error - kind = _error.InconsistentToplevel % (2, "dummy") - with raises_kind(ExtractHierarchyError, kind): - dut = traceSignals(dummy) + # this test is no longer relevant + # def testReturnVal(self, vcd_dir): + # from myhdl import ExtractHierarchyError + # from myhdl._extractHierarchy import _error + # kind = _error.InconsistentToplevel % (2, "dummy") + # with raises_kind(ExtractHierarchyError, kind): + # dut = traceSignals(dummy()) def testHierarchicalTrace1(self, vcd_dir): p = "%s.vcd" % fun.__name__ @@ -150,7 +153,7 @@ class TestTraceSigs: def testHierarchicalTrace2(self, vcd_dir): pdut = "%s.vcd" % top.__name__ psub = "%s.vcd" % fun.__name__ - dut = traceSignals(top) + dut = traceSignals(top()) assert path.exists(pdut) assert not path.exists(psub) @@ -159,14 +162,14 @@ class TestTraceSigs: def testBackupOutputFile(self, vcd_dir): p = "%s.vcd" % fun.__name__ - dut = traceSignals(fun) + dut = traceSignals(fun()) Simulation(dut).run(1000, quiet=QUIET) _simulator._tf.close() _simulator._tracing = 0 size = path.getsize(p) pbak = p + '.' + str(path.getmtime(p)) assert not path.exists(pbak) - dut = traceSignals(fun) + dut = traceSignals(fun()) _simulator._tf.close() _simulator._tracing = 0 assert path.exists(p) @@ -181,7 +184,7 @@ class TestTraceSigs: psub = "%s.vcd" % fun.__name__ pdutd = path.join(traceSignals.directory, "%s.vcd" % top.__name__) psubd = path.join(traceSignals.directory, "%s.vcd" % fun.__name__) - dut = traceSignals(top) + dut = traceSignals(top()) _simulator._tf.close() _simulator._tracing = 0 traceSignals.directory = None