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https://github.com/myhdl/myhdl.git
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augmented assigns
This commit is contained in:
jand
parent
2c6c2bf81c
commit
172ff071b4
@ -399,43 +399,40 @@ class _ConvertVisitor(_ConversionMixin):
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self.ind = self.ind[:-4]
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def binaryOp(self, node, op=None):
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pre, suf = "", ""
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prel, sufl = "", ""
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prer, sufr = "", ""
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n, o, l, r = node.vhd, node.vhdOri, node.left.vhd, node.right.vhd
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self.inferBinaryOpCasts(node, n, o, l, r, op)
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context = None
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self.write(n.pre)
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self.write("(")
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self.write(l.pre)
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self.visit(node.left, context)
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self.write(l.suf)
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self.write(" %s " % op)
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self.write(r.pre)
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self.visit(node.right, context)
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self.write(r.suf)
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self.write(")")
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self.write(n.suf)
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def inferBinaryOpCasts(self, node, n, o, l, r, op):
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ns, os, ls, rs = n.size, o.size, l.size, r.size
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ds = ns - os
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if isinstance(o, vhd_int):
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if isinstance(n, vhd_unsigned):
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pre, suf = "to_unsigned(", ", %s)" % node.vhd.size
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n.pre, n.suf = "to_unsigned(", ", %s)" % node.vhd.size
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elif isinstance(n, vhd_signed):
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pre, suf = "to_signed(", ", %s)" % node.vhd.size
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n.pre, n.suf = "to_signed(", ", %s)" % node.vhd.size
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elif isinstance(n, vhd_int):
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pass
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else:
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self.raiseError(node, "Not implemented")
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elif isinstance(l, vhd_unsigned) and isinstance(r, (vhd_int, vhd_unsigned)):
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## if op == '+':
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## print ns
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## print os
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## print ds
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if ds > 0:
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prel, sufl = "resize(", ", %s)" % ns
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l.pre, l.suf = "resize(", ", %s)" % ns
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elif ds < 0:
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pre, suf = "resize(", ", %s)" % ns
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n.pre, n.suf = "resize(", ", %s)" % ns
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context = None
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self.write(pre)
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self.write("(")
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self.write(prel)
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self.visit(node.left, context)
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self.write(sufl)
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self.write(" %s " % op)
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self.write(prer)
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self.visit(node.right, context)
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self.write(sufr)
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self.write(")")
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self.write(suf)
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def visitAdd(self, node, *args):
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self.binaryOp(node, '+')
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def visitFloorDiv(self, node, *args):
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@ -642,9 +639,9 @@ class _ConvertVisitor(_ConversionMixin):
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self.write(node.name)
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def visitAugAssign(self, node, *args):
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if node.op in ("|=", "&=", "^="):
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self.bitOpAugAssign(node, *args)
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return
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## if node.op in ("|=", "&=", "^="):
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## self.bitOpAugAssign(node, *args)
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## return
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opmap = {"+=" : "+",
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"-=" : "-",
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"*=" : "*",
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@ -660,13 +657,23 @@ class _ConvertVisitor(_ConversionMixin):
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if node.op not in opmap:
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self.raiseError(node, _error.NotSupported,
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"augmented assignment %s" % node.op)
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op = opmap[node.op]
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# XXX apparently no signed context required for augmented assigns
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n, l, r, = node.vhd, node.vhd, node.expr.vhd
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if node.op[:-1] in ('+', '-', '*' '%', '//'):
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o = node.vhdOri
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self.inferBinaryOpCasts(node, n, o, l, r, node.op[:-1])
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op = opmap[node.op]
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self.visit(node.node)
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self.write(" := ")
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self.write(n.pre)
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self.write(l.pre)
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self.visit(node.node)
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self.write(l.suf)
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self.write(" %s " % op)
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self.write(r.pre)
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self.visit(node.expr)
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self.write(r.suf)
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self.write(n.suf)
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self.write(";")
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def bitOpAugAssign(self, node, *args):
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@ -1355,37 +1362,6 @@ class _ConvertAlwaysDecoVisitor(_ConvertVisitor):
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assert self.ast.senslist
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senslist = self.ast.senslist
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senslist = self.manageEdges(node.code.nodes[0], senslist)
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## first = senslist[0]
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## if isinstance(first, _WaiterList):
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## bt = _WaiterList
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## elif isinstance(first, Signal):
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## bt = Signal
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## elif isinstance(first, delay):
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## bt = delay
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## assert bt
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## for e in senslist:
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## if not isinstance(e, bt):
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## self.raiseError(node, "base type error in sensitivity list")
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## if len(senslist) >= 2 and bt == _WaiterList:
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## ifnode = node.code.nodes[0]
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## assert isinstance(ifnode, astNode.If)
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## asyncEdges = []
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## for test, suite in ifnode.tests:
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## e = self.getEdge(test)
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## if e is None:
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## self.raiseError(node, "no edge test")
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## asyncEdges.append(e)
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## if ifnode.else_ is None:
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## self.raiseError(node, "no else test")
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## edges = []
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## for s in senslist:
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## for e in asyncEdges:
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## if s is e:
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## break
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## else:
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## edges.append(s)
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## ifnode.else_.edge = edges
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## senslist = [s.sig for s in senslist]
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singleEdge = (len(senslist) == 1) and isinstance(senslist[0], _WaiterList)
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self.write("%s: process (" % self.ast.name)
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if singleEdge:
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@ -1504,15 +1480,19 @@ class _ConvertTaskVisitor(_ConvertVisitor):
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class vhd_type(object):
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def __init__(self, size=0):
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self.size = size
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self.pre = ""
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self.suf = ""
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class vhd_std_logic(vhd_type):
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def __init__(self, size=0):
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vhd_type.__init__(self)
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self.size = 1
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def toStr(self, constr=True):
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return 'std_logic'
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class vhd_boolean(vhd_type):
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def __init__(self, size=0):
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vhd_type.__init__(self)
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self.size = 1
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def toStr(self, constr=True):
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return 'boolean'
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@ -1587,6 +1567,13 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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def visitAugAssign(self, node):
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self.visit(node.node)
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self.visit(node.expr)
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if node.op in ("|=", "&=", "^="):
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node.expr.vhd = node.node.vhd
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node.vhdlOri = node.node.vhd
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else:
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r, l = node.node.vhd, node.expr.vhd
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self.inferBinaryOpType(node, l, r, node.op)
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node.vhdOri = node.vhd
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node.vhd = node.node.vhd
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def visitCallFunc(self, node):
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@ -1647,33 +1634,38 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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self.visit(node.left)
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self.visit(node.right)
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r, l = node.right.vhd, node.left.vhd
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self.inferBinaryOpType(node, l, r, op)
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node.vhdOri = node.vhd
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def inferBinaryOpType(self, node, r, l, op=None):
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rs, ls = r.size, l.size
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if isinstance(r, vhd_signed) and isinstance(r, vhd_unsigned):
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rs += 1
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if isinstance(r, vhd_unsigned) and isinstance(r, vhd_signed):
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ls += 1
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if isinstance(r, vhd_vector) and isinstance(l, vhd_vector):
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if op in ('+', '-'):
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if op in ('+', '-', '+=', '-='):
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s = max(ls, rs)
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elif op == '%':
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elif op in ('%' '%='):
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s = rs
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elif op == '/':
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elif op in ('/', '//='):
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s = ls
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elif op == '*':
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elif op in ('*', '*='):
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s = ls + rs
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else:
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self.raiseError(node, "Not implemented: %s" % op)
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elif isinstance(l, vhd_vector) and isinstance(r, vhd_int):
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if op in ('+', '-', '%', '/'):
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if op in ('+', '-', '%', '/', '+=', '-=', '%=', '//='):
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s = ls
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elif op == '*':
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elif op in ('*' , '*='):
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s = 2 * ls
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else:
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self.raiseError(node, "Not implemented")
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elif isinstance(l, vhd_int) and isinstance(r, vhd_vector):
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if op in ('+', '-', '%', '/'):
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if op in ('+', '-', '%', '/', '+=', '-=', '%=', '//='):
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s = rs
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elif op == '*':
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elif op in ('*' , '*='):
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s = 2 * rs
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else:
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self.raiseError(node, "Not implemented: %s" % op)
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@ -1685,7 +1677,7 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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node.vhd = vhd_unsigned(s)
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else:
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node.vhd = vhd_int()
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node.vhdOri = node.vhd
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def visitAdd(self, node):
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self.binaryOp(node, op='+')
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@ -325,7 +325,8 @@ def augmOps( Bitand,
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Sub,
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Sum,
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left, right):
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var = intbv(0)[max(64, len(left) + len(right)):]
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## var = intbv(0)[min(64, len(left) + len(right)):]
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var = intbv(0)[len(left) + len(right):]
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while True:
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yield left, right
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var[:] = left
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@ -344,26 +345,28 @@ def augmOps( Bitand,
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var[:] = left
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var -= right
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Sub.next = var
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var[:] = left
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var += right
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Sum.next = var
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# FloorDiv.next = var
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## if left < 256 and right < 40:
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## var[:] = left
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## var <<= right
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## LeftShift.next = var
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## if right != 0:
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## var[:] = left
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## var %= right
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## Modulo.next = var
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## var[:] = left
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## var *= right
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## Mul.next = var
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var[:] = left
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#var *= right
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#Mul.next = var
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## var[:] = left
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## var >>= right
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## RightShift.next = var
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var[:] = left
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var += right
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Sum.next = var
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@ -419,13 +422,13 @@ def augmBench(m, n):
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print Bitand
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print Bitor
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print Bitxor
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print Sub
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print Sum
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# print FloorDiv
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## print LeftShift
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# print Modulo
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#print Mul
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## print RightShift
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# print Sub
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# print Sum
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return augmops, stimulus(), check()
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